commit b1146a242c423a1f703ccdf75f1a7c6649d60f72
author Chad Rosier <mcrosier@apple.com> Tue Nov 27 22:12:11 2012 +0000
committer Chad Rosier <mcrosier@apple.com> Tue Nov 27 22:12:11 2012 +0000
tree eaefc98e367c5d70d654b3b12645977d775e6a32
parent 4b3448b03ef28a917d47db11c69f2d42e97d11bf

[arm fast-isel] Appease the machine verifier by using the proper register
classes.
rdar://12719844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168733 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMFastISel.cpp

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 96e2ce9..e972a93 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -2595,10 +2595,12 @@
     break;
   case MVT::i8:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt)
+    if (isZExt) {
       Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
-    else
+    } else {
       Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
+      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    }
     break;
   case MVT::i1:
     if (isZExt) {