commit b181ad34869c4fa19c527ab8dfd5d438ad8b9bb3
author Jim Grosbach <grosbach@apple.com> Fri Mar 11 23:00:16 2011 +0000
committer Jim Grosbach <grosbach@apple.com> Fri Mar 11 23:00:16 2011 +0000
tree 2413d0b42eeb81cef312d3be1090b0de237bcf2e
parent dd11988c999c23eba2467e35892a2f42858c886b

80 columns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127505 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMExpandPseudoInsts.cpp

diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 0891453..a985152 100644
--- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1026,7 +1026,8 @@
       unsigned SrcReg = MI.getOperand(1).getReg();
       unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
       unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
-                                               Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
+                            Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
+                            &ARM::DPR_VFP2RegClass);
       // The lane is [0,1] for the containing DReg superregister.
       // Copy the dst/src register operands.
       MIB.addOperand(MI.getOperand(OpIdx++));