Make a new llvm/Target #include directory.
Move files from lib/CodeGen/TargetMachine to lib/Target
Move TargetData.h and TargetMachine.h to Target/{Data.h|Machine.h}
Prepare to split TargetMachine.h into several smaller files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@566 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Makefile b/lib/Target/Makefile
index ebcd23a..7fd02c6 100644
--- a/lib/Target/Makefile
+++ b/lib/Target/Makefile
@@ -1,5 +1,5 @@
LEVEL = ../..
DIRS = Sparc
+LIBRARYNAME = target
include $(LEVEL)/Makefile.common
-
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 2358687..0987572 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/InstrScheduling.h"
#include "llvm/CodeGen/SchedPriorities.h"
#include "llvm/Analysis/LiveVar/BBLiveVar.h"
-#include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Target/Machine.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Instruction.h"
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 05109cb..3c819f6 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -18,7 +18,7 @@
#include "llvm/Method.h"
#include "llvm/CodeGen/SchedGraph.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Target/Machine.h"
#include "llvm/Support/StringExtras.h"
#include <algorithm>
diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.h b/lib/Target/SparcV9/RegAlloc/RegClass.h
index 1d08502..efe1746 100644
--- a/lib/Target/SparcV9/RegAlloc/RegClass.h
+++ b/lib/Target/SparcV9/RegAlloc/RegClass.h
@@ -16,19 +16,14 @@
*/
-
-
#ifndef REG_CLASS_H
#define REG_CLASS_H
#include "llvm/CodeGen/IGNode.h"
#include "llvm/CodeGen/InterferenceGraph.h"
-#include "llvm/CodeGen/TargetMachine.h"
-
-
+#include "llvm/Target/Machine.h"
#include <stack>
-
typedef vector<unsigned int> ReservedColorListType;
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 606966d..f9a344b 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -8,7 +8,7 @@
#ifndef SPARC_INTERNALS_H
#define SPARC_INTERNALS_H
-#include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Target/Machine.h"
#include "SparcRegInfo.h"
#include <sys/types.h>
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.h b/lib/Target/SparcV9/SparcV9RegInfo.h
index 41a6d00..3ebef55 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.h
+++ b/lib/Target/SparcV9/SparcV9RegInfo.h
@@ -4,19 +4,17 @@
Purpose: Contains the description of integer register class of Sparc
*/
-
#ifndef SPARC_INT_REG_CLASS_H
#define SPARC_INT_REG_CLASS_H
-#include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Target/Machine.h"
//-----------------------------------------------------------------------------
// Integer Register Class
//-----------------------------------------------------------------------------
-
// Int register names in same order as enum in class SparcIntRegOrder
-
+//
static string const IntRegNames[] =
{ "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp
new file mode 100644
index 0000000..2e2ffd8
--- /dev/null
+++ b/lib/Target/TargetData.cpp
@@ -0,0 +1,180 @@
+//===-- TargetData.cpp - Data size & alignment routines --------------------==//
+//
+// This file defines target properties related to datatype size/offset/alignment
+// information. It uses lazy annotations to cache information about how
+// structure types are laid out and used.
+//
+// This structure should be created once, filled in if the defaults are not
+// correct and then passed around by const&. None of the members functions
+// require modification to the object.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/Data.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/ConstPoolVals.h"
+
+static inline void getTypeInfo(const Type *Ty, const TargetData *TD,
+ unsigned &Size, unsigned char &Alignment);
+
+//===----------------------------------------------------------------------===//
+// Support for StructLayout Annotation
+//===----------------------------------------------------------------------===//
+
+StructLayout::StructLayout(const StructType *ST, const TargetData &TD)
+ : Annotation(TD.getStructLayoutAID()) {
+ StructAlignment = 0;
+ StructSize = 0;
+
+ // Loop over each of the elements, placing them in memory...
+ for (StructType::ElementTypes::const_iterator
+ TI = ST->getElementTypes().begin(),
+ TE = ST->getElementTypes().end(); TI != TE; ++TI) {
+ const Type *Ty = *TI;
+ unsigned char A;
+ unsigned TySize, TyAlign;
+ getTypeInfo(Ty, &TD, TySize, A); TyAlign = A;
+
+ // Add padding if neccesary to make the data element aligned properly...
+ if (StructSize % TyAlign != 0)
+ StructSize = (StructSize/TyAlign + 1) * TyAlign; // Add padding...
+
+ // Keep track of maximum alignment constraint
+ StructAlignment = max(TyAlign, StructAlignment);
+
+ MemberOffsets.push_back(StructSize);
+ StructSize += TySize; // Consume space for this data item...
+ }
+
+ // Add padding to the end of the struct so that it could be put in an array
+ // and all array elements would be aligned correctly.
+ if (StructSize % StructAlignment != 0)
+ StructSize = (StructSize/StructAlignment + 1) * StructAlignment;
+
+ if (StructSize == 0) {
+ StructSize = 1; // Empty struct is 1 byte
+ StructAlignment = 1;
+ }
+}
+
+Annotation *TargetData::TypeAnFactory(AnnotationID AID, const Annotable *T,
+ void *D) {
+ const TargetData &TD = *(const TargetData*)D;
+ assert(AID == TD.AID && "Target data annotation ID mismatch!");
+ const Type *Ty = ((const Value *)T)->castTypeAsserting();
+ assert(Ty->isStructType() &&
+ "Can only create StructLayout annotation on structs!");
+ return new StructLayout((const StructType *)Ty, TD);
+}
+
+//===----------------------------------------------------------------------===//
+// TargetData Class Implementation
+//===----------------------------------------------------------------------===//
+
+TargetData::TargetData(const string &TargetName, unsigned char PtrSize = 8,
+ unsigned char PtrAl = 8, unsigned char DoubleAl = 8,
+ unsigned char FloatAl = 4, unsigned char LongAl = 8,
+ unsigned char IntAl = 4, unsigned char ShortAl = 2,
+ unsigned char ByteAl = 1)
+ : AID(AnnotationManager::getID("TargetData::" + TargetName)) {
+ AnnotationManager::registerAnnotationFactory(AID, TypeAnFactory, this);
+
+ PointerSize = PtrSize;
+ PointerAlignment = PtrAl;
+ DoubleAlignment = DoubleAl;
+ FloatAlignment = FloatAl;
+ LongAlignment = LongAl;
+ IntAlignment = IntAl;
+ ShortAlignment = ShortAl;
+ ByteAlignment = ByteAl;
+}
+
+TargetData::~TargetData() {
+ AnnotationManager::registerAnnotationFactory(AID, 0); // Deregister factory
+}
+
+static inline void getTypeInfo(const Type *Ty, const TargetData *TD,
+ unsigned &Size, unsigned char &Alignment) {
+ switch (Ty->getPrimitiveID()) {
+ case Type::VoidTyID:
+ case Type::BoolTyID:
+ case Type::UByteTyID:
+ case Type::SByteTyID: Size = 1; Alignment = TD->getByteAlignment(); return;
+ case Type::UShortTyID:
+ case Type::ShortTyID: Size = 2; Alignment = TD->getShortAlignment(); return;
+ case Type::UIntTyID:
+ case Type::IntTyID: Size = 4; Alignment = TD->getIntAlignment(); return;
+ case Type::ULongTyID:
+ case Type::LongTyID: Size = 8; Alignment = TD->getLongAlignment(); return;
+ case Type::FloatTyID: Size = 4; Alignment = TD->getFloatAlignment(); return;
+ case Type::DoubleTyID: Size = 8; Alignment = TD->getDoubleAlignment(); return;
+ case Type::LabelTyID:
+ case Type::PointerTyID:
+ Size = TD->getPointerSize(); Alignment = TD->getPointerAlignment();
+ return;
+ case Type::ArrayTyID: {
+ const ArrayType *ATy = (const ArrayType *)Ty;
+ assert(ATy->isSized() && "Can't get TypeInfo of an unsized array!");
+ getTypeInfo(ATy->getElementType(), TD, Size, Alignment);
+ Size *= ATy->getNumElements();
+ return;
+ }
+ case Type::StructTyID: {
+ // Get the layout annotation... which is lazily created on demand.
+ const StructLayout *Layout = TD->getStructLayout((const StructType*)Ty);
+ Size = Layout->StructSize; Alignment = Layout->StructAlignment;
+ return;
+ }
+
+ case Type::TypeTyID:
+ default:
+ assert(0 && "Bad type for getTypeInfo!!!");
+ return;
+ }
+}
+
+unsigned TargetData::getTypeSize(const Type *Ty) const {
+ unsigned Size; unsigned char Align;
+ getTypeInfo(Ty, this, Size, Align);
+ return Size;
+}
+
+unsigned char TargetData::getTypeAlignment(const Type *Ty) const {
+ unsigned Size; unsigned char Align;
+ getTypeInfo(Ty, this, Size, Align);
+ return Align;
+}
+
+unsigned TargetData::getIndexedOffset(const Type *ptrTy,
+ const vector<ConstPoolVal*> &Idx) const {
+ const PointerType *PtrTy = ptrTy->castPointerType();
+ unsigned Result = 0;
+
+ // Get the type pointed to...
+ const Type *Ty = PtrTy->getValueType();
+
+ for (unsigned CurIDX = 0; CurIDX < Idx.size(); ++CurIDX) {
+ if (const StructType *STy = Ty->dyncastStructType()) {
+ assert(Idx[CurIDX]->getType() == Type::UByteTy && "Illegal struct idx");
+ unsigned FieldNo = ((ConstPoolUInt*)Idx[CurIDX++])->getValue();
+
+ // Get structure layout information...
+ const StructLayout *Layout = getStructLayout(STy);
+
+ // Add in the offset, as calculated by the structure layout info...
+ assert(FieldNo < Layout->MemberOffsets.size() && "FieldNo out of range!");
+ Result += Layout->MemberOffsets[FieldNo];
+
+ // Update Ty to refer to current element
+ Ty = STy->getElementTypes()[FieldNo];
+
+ } else if (const ArrayType *ATy = Ty->dyncastArrayType()) {
+ assert(0 && "Loading from arrays not implemented yet!");
+ } else {
+ assert(0 && "Indexing type that is not struct or array?");
+ return 0; // Load directly through ptr
+ }
+ }
+
+ return Result;
+}
diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
new file mode 100644
index 0000000..a9e376e
--- /dev/null
+++ b/lib/Target/TargetMachine.cpp
@@ -0,0 +1,279 @@
+//===-- TargetMachine.cpp - General Target Information ---------------------==//
+//
+// This file describes the general parts of a Target machine.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/Machine.h"
+#include "llvm/DerivedTypes.h"
+
+// External object describing the machine instructions
+// Initialized only when the TargetMachine class is created
+// and reset when that class is destroyed.
+//
+const MachineInstrDescriptor* TargetInstrDescriptors = NULL;
+
+resourceId_t MachineResource::nextId = 0;
+
+static cycles_t ComputeMinGap (const InstrRUsage& fromRU,
+ const InstrRUsage& toRU);
+
+static bool RUConflict (const vector<resourceId_t>& fromRVec,
+ const vector<resourceId_t>& fromRVec);
+
+//---------------------------------------------------------------------------
+// class TargetMachine
+//
+// Purpose:
+// Machine description.
+//
+//---------------------------------------------------------------------------
+
+
+// function TargetMachine::findOptimalStorageSize
+//
+// Purpose:
+// This default implementation assumes that all sub-word data items use
+// space equal to optSizeForSubWordData, and all other primitive data
+// items use space according to the type.
+//
+unsigned int TargetMachine::findOptimalStorageSize(const Type* ty) const {
+ switch(ty->getPrimitiveID()) {
+ case Type::BoolTyID:
+ case Type::UByteTyID:
+ case Type::SByteTyID:
+ case Type::UShortTyID:
+ case Type::ShortTyID:
+ return optSizeForSubWordData;
+
+ default:
+ return DataLayout.getTypeSize(ty);
+ }
+}
+
+
+//---------------------------------------------------------------------------
+// class MachineInstructionInfo
+// Interface to description of machine instructions
+//---------------------------------------------------------------------------
+
+
+/*ctor*/
+MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
+ unsigned int _descSize,
+ unsigned int _numRealOpCodes)
+ : desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
+{
+ assert(TargetInstrDescriptors == NULL && desc != NULL);
+ TargetInstrDescriptors = desc; // initialize global variable
+}
+
+
+/*dtor*/
+MachineInstrInfo::~MachineInstrInfo()
+{
+ TargetInstrDescriptors = NULL; // reset global variable
+}
+
+
+bool
+MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
+ int64_t intValue) const
+{
+ // First, check if opCode has an immed field.
+ bool isSignExtended;
+ uint64_t maxImmedValue = this->maxImmedConstant(opCode, isSignExtended);
+ if (maxImmedValue != 0)
+ {
+ // Now check if the constant fits
+ if (intValue <= (int64_t) maxImmedValue &&
+ intValue >= -((int64_t) maxImmedValue+1))
+ return true;
+ }
+
+ return false;
+}
+
+
+//---------------------------------------------------------------------------
+// class MachineSchedInfo
+// Interface to machine description for instruction scheduling
+//---------------------------------------------------------------------------
+
+/*ctor*/
+MachineSchedInfo::MachineSchedInfo(int _numSchedClasses,
+ const MachineInstrInfo* _mii,
+ const InstrClassRUsage* _classRUsages,
+ const InstrRUsageDelta* _usageDeltas,
+ const InstrIssueDelta* _issueDeltas,
+ unsigned int _numUsageDeltas,
+ unsigned int _numIssueDeltas)
+ : numSchedClasses(_numSchedClasses),
+ mii(_mii),
+ classRUsages(_classRUsages),
+ usageDeltas(_usageDeltas),
+ issueDeltas(_issueDeltas),
+ numUsageDeltas(_numUsageDeltas),
+ numIssueDeltas(_numIssueDeltas)
+{
+}
+
+void
+MachineSchedInfo::initializeResources()
+{
+ assert(MAX_NUM_SLOTS >= (int) getMaxNumIssueTotal()
+ && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
+
+ // First, compute common resource usage info for each class because
+ // most instructions will probably behave the same as their class.
+ // Cannot allocate a vector of InstrRUsage so new each one.
+ //
+ vector<InstrRUsage> instrRUForClasses;
+ instrRUForClasses.resize(numSchedClasses);
+ for (InstrSchedClass sc=0; sc < numSchedClasses; sc++)
+ {
+ // instrRUForClasses.push_back(new InstrRUsage);
+ instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
+ instrRUForClasses[sc] = classRUsages[sc];
+ }
+
+ computeInstrResources(instrRUForClasses);
+
+ computeIssueGaps(instrRUForClasses);
+}
+
+
+void
+MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>& instrRUForClasses)
+{
+ int numOpCodes = mii->getNumRealOpCodes();
+ instrRUsages.resize(numOpCodes);
+
+ // First get the resource usage information from the class resource usages.
+ for (MachineOpCode op=0; op < numOpCodes; op++)
+ {
+ InstrSchedClass sc = getSchedClass(op);
+ assert(sc >= 0 && sc < numSchedClasses);
+ instrRUsages[op] = instrRUForClasses[sc];
+ }
+
+ // Now, modify the resource usages as specified in the deltas.
+ for (unsigned i=0; i < numUsageDeltas; i++)
+ {
+ MachineOpCode op = usageDeltas[i].opCode;
+ assert(op < numOpCodes);
+ instrRUsages[op].addUsageDelta(usageDeltas[i]);
+ }
+
+ // Then modify the issue restrictions as specified in the deltas.
+ for (unsigned i=0; i < numIssueDeltas; i++)
+ {
+ MachineOpCode op = issueDeltas[i].opCode;
+ assert(op < numOpCodes);
+ instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
+ }
+}
+
+
+void
+MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses)
+{
+ int numOpCodes = mii->getNumRealOpCodes();
+ instrRUsages.resize(numOpCodes);
+
+ assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
+ && "numOpCodes invalid for implementation of class OpCodePair!");
+
+ // First, compute issue gaps between pairs of classes based on common
+ // resources usages for each class, because most instruction pairs will
+ // usually behave the same as their class.
+ //
+ int classPairGaps[numSchedClasses][numSchedClasses];
+ for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
+ for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++)
+ {
+ int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
+ instrRUForClasses[toSC]);
+ classPairGaps[fromSC][toSC] = classPairGap;
+ }
+
+ // Now, for each pair of instructions, use the class pair gap if both
+ // instructions have identical resource usage as their respective classes.
+ // If not, recompute the gap for the pair from scratch.
+
+ longestIssueConflict = 0;
+
+ for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
+ for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++)
+ {
+ int instrPairGap =
+ (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
+ ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
+ : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
+
+ if (instrPairGap > 0)
+ {
+ issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
+ conflictLists[fromOp].push_back(toOp);
+ longestIssueConflict = max(longestIssueConflict, instrPairGap);
+ }
+ }
+}
+
+
+// Check if fromRVec and toRVec have *any* common entries.
+// Assume the vectors are sorted in increasing order.
+// Algorithm copied from function set_intersection() for sorted ranges (stl_algo.h).
+inline static bool
+RUConflict(const vector<resourceId_t>& fromRVec,
+ const vector<resourceId_t>& toRVec)
+{
+ bool commonElementFound = false;
+
+ unsigned fN = fromRVec.size(), tN = toRVec.size();
+ unsigned fi = 0, ti = 0;
+ while (fi < fN && ti < tN)
+ if (fromRVec[fi] < toRVec[ti])
+ ++fi;
+ else if (toRVec[ti] < fromRVec[fi])
+ ++ti;
+ else
+ {
+ commonElementFound = true;
+ break;
+ }
+
+ return commonElementFound;
+}
+
+
+static cycles_t
+ComputeMinGap(const InstrRUsage& fromRU, const InstrRUsage& toRU)
+{
+ cycles_t minGap = 0;
+
+ if (fromRU.numBubbles > 0)
+ minGap = fromRU.numBubbles;
+
+ if (minGap < fromRU.numCycles)
+ {
+ // only need to check from cycle `minGap' onwards
+ for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++)
+ {
+ // check if instr. #2 can start executing `gap' cycles after #1
+ // by checking for resource conflicts in each overlapping cycle
+ cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
+ for (cycles_t c = 0; c <= numOverlap-1; c++)
+ if (RUConflict(fromRU.resourcesByCycle[gap + c],
+ toRU.resourcesByCycle[c]))
+ {// conflict found so minGap must be more than `gap'
+ minGap = gap+1;
+ break;
+ }
+ }
+ }
+
+ return minGap;
+}
+
+//---------------------------------------------------------------------------