Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d817c48..ad9d853 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2322,7 +2322,8 @@
}
// fold (or x, undef) -> -1
- if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
+ if (!LegalOperations &&
+ (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
}
diff --git a/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
new file mode 100644
index 0000000..ad2810b
--- /dev/null
+++ b/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+define void @main() nounwind {
+entry:
+ store <2 x i64> undef, <2 x i64>* undef, align 16
+ %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
+ %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
+ store <16 x i8> %1, <16 x i8>* undef, align 16
+ ret void
+}