Do not lose mem_operands while lowering VLD / VST intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index 68dd503..805aad5 100644
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -491,7 +491,7 @@
; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
-define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
+define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
;CHECK: test_qqqq_regsequence_subreg
;CHECK: vld3.16
%tmp63 = extractvalue [6 x i64] %b, 5
@@ -500,8 +500,12 @@
%ins67 = or i128 %tmp65, 0
%tmp78 = bitcast i128 %ins67 to <8 x i16>
%vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
- call void @llvm.trap()
- unreachable
+ %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0
+ %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1
+ %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2
+ %tmp6 = add <8 x i16> %tmp3, %tmp4
+ %tmp7 = add <8 x i16> %tmp5, %tmp6
+ ret <8 x i16> %tmp7
}
declare void @llvm.trap() nounwind