Add stub for RAGreedy::trySplit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121736 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index aab2848..005165e 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -83,6 +83,9 @@
bool checkUncachedInterference(LiveInterval &, unsigned);
bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
+
+ unsigned trySplit(LiveInterval&, AllocationOrder&,
+ SmallVectorImpl<LiveInterval*>&);
};
} // end anonymous namespace
@@ -222,6 +225,15 @@
return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
}
+/// trySplit - Try to split VirtReg or one of its interferences, making it
+/// assignable.
+/// @return Physreg when VirtReg may be assigned and/or new SplitVRegs.
+unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
+ SmallVectorImpl<LiveInterval*>&SplitVRegs) {
+ NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
+ return 0;
+}
+
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
// Populate a list of physical register spill candidates.
@@ -266,6 +278,10 @@
PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
ReassignCands.end());
+ unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs);
+ if (PhysReg || !SplitVRegs.empty())
+ return PhysReg;
+
// Try to spill another interfering reg with less spill weight.
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
//