Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Reviewed by Chris Latter and Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index 1326ebc..1c66399 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -31,6 +31,7 @@
#include "OptParserEmitter.h"
#include "Record.h"
#include "RegisterInfoEmitter.h"
+#include "ARMDecoderEmitter.h"
#include "SubtargetEmitter.h"
#include "TGParser.h"
#include "llvm/Support/CommandLine.h"
@@ -47,6 +48,7 @@
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
+ GenARMDecoder,
GenDisassembler,
GenCallingConv,
GenClangDiagsDefs,
@@ -83,6 +85,8 @@
"Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
"Generate assembly writer"),
+ clEnumValN(GenARMDecoder, "gen-arm-decoder",
+ "Generate decoders for ARM/Thumb"),
clEnumValN(GenDisassembler, "gen-disassembler",
"Generate disassembler"),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
@@ -228,6 +232,9 @@
case GenAsmWriter:
AsmWriterEmitter(Records).run(*Out);
break;
+ case GenARMDecoder:
+ ARMDecoderEmitter(Records).run(*Out);
+ break;
case GenAsmMatcher:
AsmMatcherEmitter(Records).run(*Out);
break;