commit b6ac11cd03e9dd97b45dc97787171f942ef8e344
author Andrew Trick <atrick@apple.com> Thu Sep 26 05:53:35 2013 +0000
committer Andrew Trick <atrick@apple.com> Thu Sep 26 05:53:35 2013 +0000
tree c3a5445d795ffac70245f791c111588b6d3703ee
parent 7394a7c0c27d498fe7ff0760eeefdb83bb54a795

Added temp flag -misched-bench for staging in default changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8369fd3..6d097a6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -230,7 +230,7 @@
     const TargetLowering *TLI = IS->getTargetLowering();
     const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
 
-    if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
+    if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
         TLI->getSchedulingPreference() == Sched::Source)
       return createSourceListDAGScheduler(IS, OptLevel);
     if (TLI->getSchedulingPreference() == Sched::RegPressure)