For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90243 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 3166931..61b7705 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -152,7 +152,7 @@
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 1;
- let Inst{11-9} = 0b101;
+ let Inst{11-8} = 0b1011;
}
// Use vstmia to store a Q register as a D register pair.
@@ -164,7 +164,7 @@
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 0;
- let Inst{11-9} = 0b101;
+ let Inst{11-8} = 0b1011;
}
// VLD1 : Vector Load (multiple single elements)