Remove some unnecessary casts, and add the AssertZext case to
MaskedValueIsZero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23164 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 9158f78..c550e68 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1095,6 +1095,7 @@
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::ZERO_EXTEND:
+ case ISD::AssertZext:
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
@@ -1228,8 +1229,8 @@
case ISD::AND : return getConstant(C1 & C2, VT);
case ISD::OR : return getConstant(C1 | C2, VT);
case ISD::XOR : return getConstant(C1 ^ C2, VT);
- case ISD::SHL : return getConstant(C1 << (int)C2, VT);
- case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT);
+ case ISD::SHL : return getConstant(C1 << C2, VT);
+ case ISD::SRL : return getConstant(C1 >> C2, VT);
case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT);
default: break;
}