diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 6d7f40d..63fbb6d 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -633,9 +633,9 @@
     } else {
       /* If otherwise unadorned, default to D-form address with 0 offset: */
       if (Opc == ISD::CopyFromReg) {
-	Index = N.getOperand(1);
+        Index = N.getOperand(1);
       } else {
-	Index = N;
+        Index = N;
       }
 
       Base = CurDAG->getTargetConstant(0, Index.getValueType());
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 6bb76d8..3a399c1 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -608,7 +608,7 @@
     // specified by the operand:
     MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
     result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT,
-	                 DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
+                         DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
 
     // Handle extending loads by extending the scalar result:
     if (ExtType == ISD::SEXTLOAD) {
@@ -619,7 +619,7 @@
       unsigned NewOpc = ISD::ANY_EXTEND;
 
       if (OutVT.isFloatingPoint())
-	NewOpc = ISD::FP_EXTEND;
+        NewOpc = ISD::FP_EXTEND;
 
       result = DAG.getNode(NewOpc, OutVT, result);
     }
@@ -775,8 +775,8 @@
             DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue);
 
     result = DAG.getNode(SPUISD::SHUFB, vecVT,
-			 vectorizeOp, alignLoadVec,
-			 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
+                         vectorizeOp, alignLoadVec,
+                         DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, insertEltOp));
 
     result = DAG.getStore(the_chain, result, basePtr,
                           LN->getSrcValue(), LN->getSrcValueOffset(),
@@ -2094,7 +2094,7 @@
     DAG.getNode(SPUISD::SHUFB, VT,
                 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
                 VecOp,
-		DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
+                DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, ShufMask));
 
   return result;
 }
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index f35a42d..46e6389 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -28,8 +28,8 @@
     unsigned opc = I->getOpcode();
 
     return (opc == SPU::BR
-	    || opc == SPU::BRA
-	    || opc == SPU::BI);
+            || opc == SPU::BRA
+            || opc == SPU::BI);
   }
 
   //! Predicate for a conditional branch instruction
@@ -38,12 +38,12 @@
 
     return (opc == SPU::BRNZr32
             || opc == SPU::BRNZv4i32
-	    || opc == SPU::BRZr32
-	    || opc == SPU::BRZv4i32
-	    || opc == SPU::BRHNZr16
-	    || opc == SPU::BRHNZv8i16
-	    || opc == SPU::BRHZr16
-	    || opc == SPU::BRHZv8i16);
+            || opc == SPU::BRZr32
+            || opc == SPU::BRZv4i32
+            || opc == SPU::BRHNZr16
+            || opc == SPU::BRHNZv8i16
+            || opc == SPU::BRHZr16
+            || opc == SPU::BRHZv8i16);
   }
 }
 
@@ -531,8 +531,8 @@
  */
 bool
 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-			    MachineBasicBlock *&FBB,
-			    SmallVectorImpl<MachineOperand> &Cond) const {
+                            MachineBasicBlock *&FBB,
+                            SmallVectorImpl<MachineOperand> &Cond) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -621,8 +621,8 @@
 
 unsigned
 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-			   MachineBasicBlock *FBB,
-			   const SmallVectorImpl<MachineOperand> &Cond) const {
+                           MachineBasicBlock *FBB,
+                           const SmallVectorImpl<MachineOperand> &Cond) const {
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 2 || Cond.size() == 0) &&
diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h
index 7bbdfad..0ec3b5f 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.h
+++ b/lib/Target/CellSPU/SPUInstrInfo.h
@@ -103,14 +103,14 @@
     bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 
     virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
-			       MachineBasicBlock *&FBB,
-			       SmallVectorImpl<MachineOperand> &Cond) const;
+                               MachineBasicBlock *&FBB,
+                               SmallVectorImpl<MachineOperand> &Cond) const;
 
     virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 
     virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-			      MachineBasicBlock *FBB,
-			      const SmallVectorImpl<MachineOperand> &Cond) const;
+                              MachineBasicBlock *FBB,
+                              const SmallVectorImpl<MachineOperand> &Cond) const;
    };
 }
 
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 8db2fa7..05b31bb 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -624,25 +624,25 @@
 
 class AIInst<dag OOL, dag IOL, list<dag> pattern>:
     RI10Form<0b00111000, OOL, IOL,
-	     "ai\t$rT, $rA, $val", IntegerOp,
-	     pattern>;
+             "ai\t$rT, $rA, $val", IntegerOp,
+             pattern>;
 
 class AIVecInst<ValueType vectype, PatLeaf immpred>:
     AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
-	    [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
+            [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
 
 class AIFPVecInst<ValueType vectype, PatLeaf immpred>:
     AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
-	    [/* no pattern */]>;
+            [/* no pattern */]>;
 
 class AIRegInst<RegisterClass rclass, PatLeaf immpred>:
     AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
-	   [(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
+           [(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
 
 // This is used to add epsilons to floating point numbers in the f32 fdiv code:
 class AIFPInst<RegisterClass rclass, PatLeaf immpred>:
     AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
-	   [/* no pattern */]>;
+           [/* no pattern */]>;
 
 multiclass AddImmediate {
   def v4i32: AIVecInst<v4i32, v4i32SExt10Imm>;
@@ -1969,11 +1969,11 @@
   def v2i64_vcond: SELBVecCondInst<v2i64>;
 
   def v4f32_cond:
-	SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
-		 [(set (v4f32 VECREG:$rT),
-		       (select (v4i32 VECREG:$rC),
-			       (v4f32 VECREG:$rB),
-			       (v4f32 VECREG:$rA)))]>;
+        SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
+                 [(set (v4f32 VECREG:$rT),
+                       (select (v4i32 VECREG:$rC),
+                               (v4f32 VECREG:$rB),
+                               (v4f32 VECREG:$rA)))]>;
 
   // SELBr64_cond is defined in SPU64InstrInfo.td
   def r32_cond:   SELBRegCondInst<R32C, R32C>;
@@ -3260,7 +3260,7 @@
                                     (v4i32 v4i32SExt16Imm:$val)))]>;
 
   def f32:   CGTIInst<(outs R32C:$rT), (ins R32FP:$rA, s10imm_i32:$val),
-  		      [/* no pattern */]>;
+                      [/* no pattern */]>;
 }
 
 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
diff --git a/lib/Target/CellSPU/SPUMathInstr.td b/lib/Target/CellSPU/SPUMathInstr.td
index 64548fd..80ebde3 100644
--- a/lib/Target/CellSPU/SPUMathInstr.td
+++ b/lib/Target/CellSPU/SPUMathInstr.td
@@ -66,15 +66,15 @@
 def DivEstf32: CodeFrag<(FMf32 R32FP:$rA, Interpf32.Fragment)>;
 // Newton-Raphson iteration
 def NRaphf32: CodeFrag<(FMAf32 (FNMSf32 DivEstf32.Fragment, R32FP:$rB, R32FP:$rA),
-		  	       Interpf32.Fragment,
-	  	  	       DivEstf32.Fragment)>;
+                               Interpf32.Fragment,
+                               DivEstf32.Fragment)>;
 // Epsilon addition
 def Epsilonf32: CodeFrag<(AIf32 NRaphf32.Fragment, 1)>;
 
 def : Pat<(fdiv R32FP:$rA, R32FP:$rB),
-	  (SELBf32_cond NRaphf32.Fragment,
-			Epsilonf32.Fragment,
-			(CGTIf32 (FNMSf32 R32FP:$rB, Epsilonf32.Fragment, R32FP:$rA), -1))>;
+          (SELBf32_cond NRaphf32.Fragment,
+                        Epsilonf32.Fragment,
+                        (CGTIf32 (FNMSf32 R32FP:$rB, Epsilonf32.Fragment, R32FP:$rA), -1))>;
 
 // Reciprocal estimate and interpolation
 def Interpv4f32: CodeFrag<(FIv4f32 (v4f32 VECREG:$rB), (FRESTv4f32 (v4f32 VECREG:$rB)))>;
@@ -82,16 +82,16 @@
 def DivEstv4f32: CodeFrag<(FMv4f32 (v4f32 VECREG:$rA), Interpv4f32.Fragment)>;
 // Newton-Raphson iteration
 def NRaphv4f32: CodeFrag<(FMAv4f32 (FNMSv4f32 DivEstv4f32.Fragment,
-					      (v4f32 VECREG:$rB),
-					      (v4f32 VECREG:$rA)),
-		  	           Interpv4f32.Fragment,
-	  	  	           DivEstv4f32.Fragment)>;
+                                              (v4f32 VECREG:$rB),
+                                              (v4f32 VECREG:$rA)),
+                                   Interpv4f32.Fragment,
+                                   DivEstv4f32.Fragment)>;
 // Epsilon addition
 def Epsilonv4f32: CodeFrag<(AIv4f32 NRaphv4f32.Fragment, 1)>;
 
 def : Pat<(fdiv (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
-	  (SELBv4f32_cond NRaphv4f32.Fragment,
-			Epsilonv4f32.Fragment,
-			(CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
-					      Epsilonv4f32.Fragment,
-					      (v4f32 VECREG:$rA)), -1))>;
+          (SELBv4f32_cond NRaphv4f32.Fragment,
+                        Epsilonv4f32.Fragment,
+                        (CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
+                                              Epsilonv4f32.Fragment,
+                                              (v4f32 VECREG:$rA)), -1))>;