commit b921f1b731ffff11d130d561a8880e216e4ace78
author Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 23:08:46 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 23:08:46 2005 +0000
tree 581180a3942c8438543f5fe5bed5225220d37a8f
parent 2729e614fa85347483d2f3ab209ebbc9a4e88bcd

fix yet more regressions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24308 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index ec3479d..1127f8b 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1530,7 +1530,7 @@
             N.getOperand(0).getValueType() == MVT::f64 &&
             "only f64 to f32 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
+    BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_EXTEND: