Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp
index e6ec43e..2efb800 100644
--- a/lib/CodeGen/DwarfWriter.cpp
+++ b/lib/CodeGen/DwarfWriter.cpp
@@ -968,7 +968,7 @@
/// EmitFrameMoves - Emit frame instructions to describe the layout of the
/// frame.
void EmitFrameMoves(const char *BaseLabel, unsigned BaseLabelID,
- const std::vector<MachineMove> &Moves) {
+ const std::vector<MachineMove> &Moves, bool isEH) {
int stackGrowth =
Asm->TM.getFrameInfo()->getStackGrowthDirection() ==
TargetFrameInfo::StackGrowsUp ?
@@ -1010,7 +1010,7 @@
} else {
Asm->EmitInt8(DW_CFA_def_cfa);
Asm->EOL("DW_CFA_def_cfa");
- Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister()));
+ Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH));
Asm->EOL("Register");
}
@@ -1026,13 +1026,13 @@
if (Dst.isRegister()) {
Asm->EmitInt8(DW_CFA_def_cfa_register);
Asm->EOL("DW_CFA_def_cfa_register");
- Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister()));
+ Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH));
Asm->EOL("Register");
} else {
assert(0 && "Machine move no supported yet.");
}
} else {
- unsigned Reg = RI->getDwarfRegNum(Src.getRegister());
+ unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH);
int Offset = Dst.getOffset() / stackGrowth;
if (Offset < 0) {
@@ -1340,7 +1340,7 @@
/// provided.
void AddAddress(DIE *Die, unsigned Attribute,
const MachineLocation &Location) {
- unsigned Reg = RI->getDwarfRegNum(Location.getRegister());
+ unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false);
DIEBlock *Block = new DIEBlock();
if (Location.isRegister()) {
@@ -2370,13 +2370,13 @@
Asm->EOL("CIE Code Alignment Factor");
Asm->EmitSLEB128Bytes(stackGrowth);
Asm->EOL("CIE Data Alignment Factor");
- Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister()));
+ Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false));
Asm->EOL("CIE RA Column");
std::vector<MachineMove> Moves;
RI->getInitialFrameState(Moves);
- EmitFrameMoves(NULL, 0, Moves);
+ EmitFrameMoves(NULL, 0, Moves, false);
Asm->EmitAlignment(2);
EmitLabel("debug_frame_common_end", 0);
@@ -2409,7 +2409,7 @@
"func_begin", DebugFrameInfo.Number);
Asm->EOL("FDE address range");
- EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves);
+ EmitFrameMoves("func_begin", DebugFrameInfo.Number, DebugFrameInfo.Moves, false);
Asm->EmitAlignment(2);
EmitLabel("debug_frame_end", DebugFrameInfo.Number);
@@ -2817,7 +2817,7 @@
Asm->EOL("CIE Code Alignment Factor");
Asm->EmitSLEB128Bytes(stackGrowth);
Asm->EOL("CIE Data Alignment Factor");
- Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister()));
+ Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true));
Asm->EOL("CIE RA Column");
// If there is a personality, we need to indicate the functions location.
@@ -2853,7 +2853,7 @@
// Indicate locations of general callee saved registers in frame.
std::vector<MachineMove> Moves;
RI->getInitialFrameState(Moves);
- EmitFrameMoves(NULL, 0, Moves);
+ EmitFrameMoves(NULL, 0, Moves, true);
Asm->EmitAlignment(2);
EmitLabel("eh_frame_common_end", Index);
@@ -2915,7 +2915,7 @@
// Indicate locations of function specific callee saved registers in
// frame.
- EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves);
+ EmitFrameMoves("eh_func_begin", EHFrameInfo.Number, EHFrameInfo.Moves, true);
Asm->EmitAlignment(2);
EmitLabel("eh_frame_end", EHFrameInfo.Number);
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index b4cd0c7..b5c04ba 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -1660,7 +1660,7 @@
return 0;
}
-int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index 7d25fdc..b1110db 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -118,7 +118,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 6cf9df7..3d1747e 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -480,7 +480,7 @@
return 0;
}
-int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h
index cd7d475..6275cb4 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -93,7 +93,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
static std::string getPrettyName(unsigned reg);
};
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index a1c4e1e..af1af31 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -451,7 +451,7 @@
return 0;
}
-int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index d30e28e..3f86a4c 100644
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -85,7 +85,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
};
} // End llvm namespace
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index ed9f7e2..9dc8563 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -539,7 +539,7 @@
}
int MipsRegisterInfo::
-getDwarfRegNum(unsigned RegNum) const {
+getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h
index 28f6936..636ffb9 100644
--- a/lib/Target/Mips/MipsRegisterInfo.h
+++ b/lib/Target/Mips/MipsRegisterInfo.h
@@ -97,7 +97,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index cac3d79..950d440 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1277,7 +1277,7 @@
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
}
-int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 8dd86e5..776d11c 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -117,7 +117,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm
diff --git a/lib/Target/PowerPC/PPCTargetAsmInfo.cpp b/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
index 992b090..6b43ecb 100644
--- a/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
+++ b/lib/Target/PowerPC/PPCTargetAsmInfo.cpp
@@ -58,7 +58,7 @@
UsedDirective = "\t.no_dead_strip\t";
WeakRefDirective = "\t.weak_reference\t";
HiddenDirective = "\t.private_extern\t";
- SupportsExceptionHandling = false;
+ SupportsExceptionHandling = true;
NeedsIndirectEncoding = true;
BSSSection = 0;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 54afcca..f3e2ff8 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -333,7 +333,7 @@
return 0;
}
-int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
+int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 267ce25..dec01e0 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -97,7 +97,7 @@
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 8102ce6..cf1dda4 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -384,7 +384,6 @@
/// e.g. r8, xmm8, etc.
bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
if (!MO.isRegister()) return false;
- unsigned RegNo = MO.getReg();
switch (MO.getReg()) {
default: break;
case X86::R8: case X86::R9: case X86::R10: case X86::R11:
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index ee754df..71f8d0e 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -657,7 +657,7 @@
// getDwarfRegNum - This function maps LLVM register identifiers to the
// Dwarf specific numbering, used in debug info and exception tables.
-int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
+int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = DWARFFlavour::X86_64;
if (!Subtarget->is64Bit()) {
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 3090288..18e8b90 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -87,7 +87,7 @@
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
/// (created by TableGen) for target dependencies.
- int getDwarfRegNum(unsigned RegNum) const;
+ int getDwarfRegNum(unsigned RegNum, bool isEH) const;
/// Code Generation virtual methods...
///
diff --git a/lib/Target/X86/X86TargetAsmInfo.cpp b/lib/Target/X86/X86TargetAsmInfo.cpp
index 05cf2bf..060e00d 100644
--- a/lib/Target/X86/X86TargetAsmInfo.cpp
+++ b/lib/Target/X86/X86TargetAsmInfo.cpp
@@ -101,8 +101,7 @@
DwarfMacInfoSection = ".section __DWARF,__debug_macinfo,regular,debug";
// Exceptions handling
- if (!Subtarget->is64Bit())
- SupportsExceptionHandling = true;
+ SupportsExceptionHandling = true;
AbsoluteEHSectionOffsets = false;
DwarfEHFrameSection =
".section __TEXT,__eh_frame,coalesced,no_toc+strip_static_syms+live_support";