Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts
into v4i16 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8bfa574..85788ef 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -604,6 +604,8 @@
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
+
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
}
if (Subtarget->hasSSE1()) {
diff --git a/test/CodeGen/X86/mmx-pinsrw.ll b/test/CodeGen/X86/mmx-pinsrw.ll
new file mode 100644
index 0000000..f1d04fa
--- /dev/null
+++ b/test/CodeGen/X86/mmx-pinsrw.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep pinsrw | count 1
+; PR2562
+
+external global i16 ; <i16*>:0 [#uses=1]
+external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2]
+
+declare void @abort()
+
+define void @""() {
+ load i16* @0 ; <i16>:1 [#uses=1]
+ load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1]
+ insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1]
+ store <4 x i16> %3, <4 x i16>* @1
+ ret void
+}