commit b9e8f97aef725324724d9e59e55dbafec02c79e9
author Misha Brukman <brukman+llvm@gmail.com> Wed Jun 30 21:54:12 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Wed Jun 30 21:54:12 2004 +0000
tree 05f1ac26dd094efc2f72e9fc1871c6b97ae4c50a
parent ea091264144add21bbd29791a914ed30e44ff1c1

* Inquire about the number of operands from the instruction directly
* Only check for a register if we are sure the instruction has one allocated


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14509 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCAsmPrinter.cpp

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 0d519ee..b06eb4b 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -498,7 +498,8 @@
   const TargetInstrDescriptor &Desc = TII.get(Opcode);
   unsigned int i;
 
-  unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
+  unsigned int ArgCount = MI->getNumOperands();
+    //Desc.TSFlags & PPC32II::ArgCountMask;
   unsigned int ArgType[] = {
     (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask,
     (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask,
@@ -554,7 +555,8 @@
     O << ", ";
     printOp(MI->getOperand(1));
     O << "(";
-    if (MI->getOperand(2).getReg() == PPC32::R0)
+    if (MI->getOperand(2).hasAllocatedReg() &&
+        MI->getOperand(2).getReg() == PPC32::R0)
       O << "0";
     else
       printOp(MI->getOperand(2));