Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp
index 8d9e891..c43ca0d 100644
--- a/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -81,10 +81,10 @@
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.isRegister()) {
+ if (MO.isReg()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
- } else if (MO.isImmediate()) {
+ } else if (MO.isImm()) {
O << MO.getImm();
} else {
printOp(MO);
@@ -186,8 +186,8 @@
printMemRegImmS10(const MachineInstr *MI, unsigned OpNo)
{
const MachineOperand &MO = MI->getOperand(OpNo);
- assert(MO.isImmediate()
- && "printMemRegImmS10 first operand is not immedate");
+ assert(MO.isImm() &&
+ "printMemRegImmS10 first operand is not immedate");
printS10ImmOperand(MI, OpNo);
O << "(";
printOperand(MI, OpNo+1);
@@ -198,11 +198,11 @@
printAddr256K(const MachineInstr *MI, unsigned OpNo)
{
/* Note: operand 1 is an offset or symbol name. */
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
} else {
printOp(MI->getOperand(OpNo));
- if (MI->getOperand(OpNo+1).isImmediate()) {
+ if (MI->getOperand(OpNo+1).isImm()) {
int displ = int(MI->getOperand(OpNo+1).getImm());
if (displ > 0)
O << "+" << displ;
@@ -222,7 +222,7 @@
}
void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
} else {
printOp(MI->getOperand(OpNo));
@@ -231,7 +231,7 @@
}
void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
} else {
printOp(MI->getOperand(OpNo));
@@ -245,7 +245,7 @@
}
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 16)
&& "Invalid negated immediate rotate 7-bit argument");
@@ -256,7 +256,7 @@
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 32)
&& "Invalid negated immediate rotate 7-bit argument");
@@ -372,9 +372,9 @@
default: return true; // Unknown modifier.
case 'L': // Write second word of DImode reference.
// Verify that this operand has two consecutive registers.
- if (!MI->getOperand(OpNo).isRegister() ||
+ if (!MI->getOperand(OpNo).isReg() ||
OpNo+1 == MI->getNumOperands() ||
- !MI->getOperand(OpNo+1).isRegister())
+ !MI->getOperand(OpNo+1).isReg())
return true;
++OpNo; // Return the high-part.
break;
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 02490e9..cc562eb 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -60,9 +60,9 @@
case SPU::AHIr16:
case SPU::AIvec:
assert(MI.getNumOperands() == 3 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
- MI.getOperand(2).isImmediate() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
+ MI.getOperand(2).isImm() &&
"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
@@ -73,10 +73,10 @@
case SPU::AIr32:
assert(MI.getNumOperands() == 3 &&
"wrong number of operands to AIr32");
- if (MI.getOperand(0).isRegister() &&
- (MI.getOperand(1).isRegister() ||
- MI.getOperand(1).isFrameIndex()) &&
- (MI.getOperand(2).isImmediate() &&
+ if (MI.getOperand(0).isReg() &&
+ (MI.getOperand(1).isReg() ||
+ MI.getOperand(1).isFI()) &&
+ (MI.getOperand(2).isImm() &&
MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
@@ -103,9 +103,9 @@
case SPU::ORf32:
case SPU::ORf64:
assert(MI.getNumOperands() == 3 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
- MI.getOperand(2).isRegister() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
+ MI.getOperand(2).isReg() &&
"invalid SPU OR(vec|r32|r64|gprc) instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
@@ -136,8 +136,8 @@
case SPU::LQXr64:
case SPU::LQXr32:
case SPU::LQXr16:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFrameIndex()) {
+ if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
@@ -170,8 +170,8 @@
case SPU::STQXr32:
case SPU::STQXr16:
// case SPU::STQXr8:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFrameIndex()) {
+ if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
@@ -273,7 +273,7 @@
cerr << "storeRegToAddr() invoked!\n";
abort();
- if (Addr[0].isFrameIndex()) {
+ if (Addr[0].isFI()) {
/* do what storeRegToStackSlot does here */
} else {
unsigned Opc = 0;
@@ -297,9 +297,9 @@
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
- if (MO.isRegister())
+ if (MO.isReg())
MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
+ else if (MO.isImm())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getIndex());
@@ -358,7 +358,7 @@
cerr << "loadRegToAddr() invoked!\n";
abort();
- if (Addr[0].isFrameIndex()) {
+ if (Addr[0].isFI()) {
/* do what loadRegFromStackSlot does here... */
} else {
unsigned Opc = 0;
@@ -383,9 +383,9 @@
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
- if (MO.isRegister())
+ if (MO.isReg())
MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
+ else if (MO.isImm())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getIndex());
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 882f79f..eff6d6a 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -328,7 +328,7 @@
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo *MFI = MF.getFrameInfo();
- while (!MI.getOperand(i).isFrameIndex()) {
+ while (!MI.getOperand(i).isFI()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
}