Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index d8451bd..d164066 100644
--- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -123,9 +123,9 @@
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.isRegister()) {
+ if (MO.isReg()) {
printRegister(MO, false);
- } else if (MO.isImmediate()) {
+ } else if (MO.isImm()) {
O << MO.getImm();
} else {
printOp(MO);
@@ -160,7 +160,7 @@
O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
O << (short)(MI->getOperand(OpNo).getImm()*4);
} else {
O << "lo16(";
@@ -174,7 +174,7 @@
void printBranchOperand(const MachineInstr *MI, unsigned OpNo) {
// Branches can take an immediate operand. This is used by the branch
// selection pass to print $+8, an eight byte displacement from the PC.
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
O << "$+" << MI->getOperand(OpNo).getImm()*4;
} else {
printOp(MI->getOperand(OpNo));
@@ -214,7 +214,7 @@
O << "\"L" << getFunctionNumber() << "$pb\":";
}
void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
} else {
if (Subtarget.isDarwin()) O << "ha16(";
@@ -228,7 +228,7 @@
}
}
void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate()) {
+ if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo);
} else {
if (Subtarget.isDarwin()) O << "lo16(";
@@ -250,7 +250,7 @@
void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
printSymbolLo(MI, OpNo);
O << '(';
- if (MI->getOperand(OpNo+1).isRegister() &&
+ if (MI->getOperand(OpNo+1).isReg() &&
MI->getOperand(OpNo+1).getReg() == PPC::R0)
O << "0";
else
@@ -258,12 +258,12 @@
O << ')';
}
void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) {
- if (MI->getOperand(OpNo).isImmediate())
+ if (MI->getOperand(OpNo).isImm())
printS16X4ImmOperand(MI, OpNo);
else
printSymbolLo(MI, OpNo);
O << '(';
- if (MI->getOperand(OpNo+1).isRegister() &&
+ if (MI->getOperand(OpNo+1).isReg() &&
MI->getOperand(OpNo+1).getReg() == PPC::R0)
O << "0";
else
@@ -443,16 +443,16 @@
return false;
case 'L': // Write second word of DImode reference.
// Verify that this operand has two consecutive registers.
- if (!MI->getOperand(OpNo).isRegister() ||
+ if (!MI->getOperand(OpNo).isReg() ||
OpNo+1 == MI->getNumOperands() ||
- !MI->getOperand(OpNo+1).isRegister())
+ !MI->getOperand(OpNo+1).isReg())
return true;
++OpNo; // Return the high-part.
break;
case 'I':
// Write 'i' if an integer constant, otherwise nothing. Used to print
// addi vs add, etc.
- if (MI->getOperand(OpNo).isImmediate())
+ if (MI->getOperand(OpNo).isImm())
O << "i";
return false;
}
@@ -467,7 +467,7 @@
const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
- if (MI->getOperand(OpNo).isRegister())
+ if (MI->getOperand(OpNo).isReg())
printMemRegReg(MI, OpNo);
else
printMemRegImm(MI, OpNo);
diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp
index 2fc5b3c..add37e1 100644
--- a/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -103,7 +103,7 @@
unsigned MBBStartOffset = 0;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
- if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
+ if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
MBBStartOffset += TII->GetInstSizeInBytes(I);
continue;
}
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index a77c726..f80442f 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -126,7 +126,7 @@
unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
- if (MO.isRegister()) {
+ if (MO.isReg()) {
rv = PPCRegisterInfo::getRegisterNumbering(MO.getReg());
// Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
@@ -135,10 +135,10 @@
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
rv = 0x80 >> rv;
}
- } else if (MO.isImmediate()) {
+ } else if (MO.isImm()) {
rv = MO.getImm();
- } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
- MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
+ } else if (MO.isGlobal() || MO.isSymbol() ||
+ MO.isCPI() || MO.isJTI()) {
unsigned Reloc = 0;
if (MI.getOpcode() == PPC::BL_Macho || MI.getOpcode() == PPC::BL8_Macho ||
MI.getOpcode() == PPC::BL_ELF || MI.getOpcode() == PPC::BL8_ELF ||
@@ -193,18 +193,18 @@
}
MachineRelocation R;
- if (MO.isGlobalAddress()) {
+ if (MO.isGlobal()) {
R = MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
MO.getGlobal(), 0,
isa<Function>(MO.getGlobal()));
- } else if (MO.isExternalSymbol()) {
+ } else if (MO.isSymbol()) {
R = MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, MO.getSymbolName(), 0);
- } else if (MO.isConstantPoolIndex()) {
+ } else if (MO.isCPI()) {
R = MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getIndex(), 0);
} else {
- assert(MO.isJumpTableIndex());
+ assert(MO.isJTI());
R = MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Reloc, MO.getIndex(), 0);
}
@@ -220,7 +220,7 @@
}
MCE.addRelocation(R);
- } else if (MO.isMachineBasicBlock()) {
+ } else if (MO.isMBB()) {
unsigned Reloc = 0;
unsigned Opcode = MI.getOpcode();
if (Opcode == PPC::B || Opcode == PPC::BL_Macho ||
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 27899a7..ca65feb 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -47,9 +47,9 @@
if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
- MI.getOperand(2).isRegister() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
+ MI.getOperand(2).isReg() &&
"invalid PPC OR instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
@@ -58,19 +58,19 @@
}
} else if (oc == PPC::ADDI) { // addi r1, r2, 0
assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(2).isImmediate() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(2).isImm() &&
"invalid PPC ADDI instruction!");
- if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
+ if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
} else if (oc == PPC::ORI) { // ori r1, r2, 0
assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
- MI.getOperand(2).isImmediate() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
+ MI.getOperand(2).isImm() &&
"invalid PPC ORI instruction!");
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
@@ -80,16 +80,16 @@
} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
oc == PPC::FMRSD) { // fmr r1, r2
assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
"invalid PPC FMR instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
assert(MI.getNumOperands() >= 2 &&
- MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
+ MI.getOperand(0).isReg() &&
+ MI.getOperand(1).isReg() &&
"invalid PPC MCRF instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
@@ -106,8 +106,8 @@
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFrameIndex()) {
+ if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
@@ -124,8 +124,8 @@
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
- if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFrameIndex()) {
+ if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFI()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
@@ -478,7 +478,7 @@
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{
- if (Addr[0].isFrameIndex()) {
+ if (Addr[0].isFI()) {
if (StoreRegToStackSlot(MF, SrcReg, isKill,
Addr[0].getIndex(), RC, NewMIs)) {
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@@ -507,9 +507,9 @@
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
- if (MO.isRegister())
+ if (MO.isReg())
MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
+ else if (MO.isImm())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getIndex());
@@ -617,7 +617,7 @@
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs)const{
- if (Addr[0].isFrameIndex()) {
+ if (Addr[0].isFI()) {
LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
return;
}
@@ -642,9 +642,9 @@
MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
- if (MO.isRegister())
+ if (MO.isReg())
MIB.addReg(MO.getReg());
- else if (MO.isImmediate())
+ else if (MO.isImm())
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getIndex());
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 014925e..586ad6b 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -629,7 +629,7 @@
// Find out which operand is the frame index.
unsigned FIOperandNo = 0;
- while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
+ while (!MI.getOperand(FIOperandNo).isFI()) {
++FIOperandNo;
assert(FIOperandNo != MI.getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
@@ -1242,7 +1242,7 @@
if (UsesTCRet) {
int MaxTCRetDelta = FI->getTailCallSPDelta();
MachineOperand &StackAdjust = MBBI->getOperand(1);
- assert( StackAdjust.isImmediate() && "Expecting immediate value.");
+ assert(StackAdjust.isImm() && "Expecting immediate value.");
// Adjust stack pointer.
int StackAdj = StackAdjust.getImm();
int Delta = StackAdj - MaxTCRetDelta;
@@ -1368,7 +1368,7 @@
} else if (RetOpcode == PPC::TCRETURNri) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- assert(JumpTarget.isRegister() && "Expecting register operand.");
+ assert(JumpTarget.isReg() && "Expecting register operand.");
BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR));
} else if (RetOpcode == PPC::TCRETURNai) {
MBBI = prior(MBB.end());
@@ -1382,7 +1382,7 @@
} else if (RetOpcode == PPC::TCRETURNri8) {
MBBI = prior(MBB.end());
MachineOperand &JumpTarget = MBBI->getOperand(0);
- assert(JumpTarget.isRegister() && "Expecting register operand.");
+ assert(JumpTarget.isReg() && "Expecting register operand.");
BuildMI(MBB, MBBI, TII.get(PPC::TAILBCTR8));
} else if (RetOpcode == PPC::TCRETURNai8) {
MBBI = prior(MBB.end());