diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 094b9ce..10a3565 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -433,8 +433,7 @@
       for (unsigned j = i+1; j < e; ++j) {
         MachineOperand &MO2 = MI->getOperand(j);
         if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
-            TII->getOperandConstraint(MI->getOpcode(), j,
-                                      TargetInstrInfo::TIED_TO) == (int)i)
+            TII->getOperandConstraint(MI->getOpcode(),j,TOI::TIED_TO) == (int)i)
           return true;
       }
     }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index e72cdc6..42b587f 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -127,8 +127,7 @@
     if (MainNode->isTargetOpcode()) {
       unsigned Opc = MainNode->getTargetOpcode();
       for (unsigned i = 0, ee = TII->getNumOperands(Opc); i != ee; ++i) {
-        if (TII->getOperandConstraint(Opc, i,
-                                      TargetInstrInfo::TIED_TO) != -1) {
+        if (TII->getOperandConstraint(Opc, i, TOI::TIED_TO) != -1) {
           SU->isTwoAddress = true;
           break;
         }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 4b36a8f..e0a0499 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -128,8 +128,7 @@
       unsigned NumRes = CountResults(SU->Node);
       unsigned NumOps = CountOperands(SU->Node);
       for (unsigned j = 0; j != NumOps; ++j) {
-        if (TII->getOperandConstraint(Opc, j+NumRes,
-                                      TargetInstrInfo::TIED_TO) == -1)
+        if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
           continue;
 
         SDNode *OpN = SU->Node->getOperand(j).Val;
@@ -498,8 +497,7 @@
       unsigned NumRes = ScheduleDAG::CountResults(SU1->Node);
       unsigned NumOps = ScheduleDAG::CountOperands(SU1->Node);
       for (unsigned i = 0; i != NumOps; ++i) {
-        if (TII->getOperandConstraint(Opc, i+NumRes,
-                                      TargetInstrInfo::TIED_TO) == -1)
+        if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) == -1)
           continue;
         if (SU1->Node->getOperand(i).isOperand(SU2->Node))
           return true;
@@ -667,8 +665,7 @@
     unsigned NumRes = ScheduleDAG::CountResults(SU->Node);
     unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
     for (unsigned i = 0; i != NumOps; ++i) {
-      if (TII->getOperandConstraint(Opc, i+NumRes,
-                                    TargetInstrInfo::TIED_TO) != -1) {
+      if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(i).Val;
         if (Op == (*SUnitMap)[DU])
           return true;
@@ -698,8 +695,7 @@
     unsigned NumRes = ScheduleDAG::CountResults(Node);
     unsigned NumOps = ScheduleDAG::CountOperands(Node);
     for (unsigned j = 0; j != NumOps; ++j) {
-      if (TII->getOperandConstraint(Opc, j+NumRes,
-                                    TargetInstrInfo::TIED_TO) != -1) {
+      if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
         SDNode *DU = SU->Node->getOperand(j).Val;
         SUnit *DUSU = (*SUnitMap)[DU];
         if (!DUSU) continue;
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index b81ced2..335a7e4 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -79,8 +79,8 @@
 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
   DOUT << "Machine Function\n";
   const TargetMachine &TM = MF.getTarget();
-  const MRegisterInfo &MRI = *TM.getRegisterInfo();
   const TargetInstrInfo &TII = *TM.getInstrInfo();
+  const MRegisterInfo &MRI = *TM.getRegisterInfo();
   LiveVariables &LV = getAnalysis<LiveVariables>();
 
   bool MadeChange = false;
@@ -92,11 +92,11 @@
        mbbi != mbbe; ++mbbi) {
     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
          mi != me; ++mi) {
-      unsigned opcode = mi->getOpcode();
+      const TargetInstrDescriptor *TID = mi->getInstrDescriptor();
 
       bool FirstTied = true;
-      for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
-        int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO);
+      for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
+        int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
         if (ti == -1)
           continue;
 
@@ -139,13 +139,11 @@
           // allow us to coalesce A and B together, eliminating the copy we are
           // about to insert.
           if (!LV.KillsRegister(mi, regB)) {
-            const TargetInstrDescriptor &TID = TII.get(opcode);
-
             // If this instruction is commutative, check to see if C dies.  If
             // so, swap the B and C operands.  This makes the live ranges of A
             // and C joinable.
             // FIXME: This code also works for A := B op C instructions.
-            if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
+            if ((TID->Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
               assert(mi->getOperand(3-si).isRegister() &&
                      "Not a proper commutative instruction!");
               unsigned regC = mi->getOperand(3-si).getReg();
@@ -173,20 +171,17 @@
 
             // If this instruction is potentially convertible to a true
             // three-address instruction,
-            if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
+            if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR)
               // FIXME: This assumes there are no more operands which are tied
               // to another register.
 #ifndef NDEBUG
-              for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i)
-                assert(TII.getOperandConstraint(opcode, i,
-                                                TargetInstrInfo::TIED_TO) == -1);
+              for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
+                assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
 #endif
 
-              if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
+              if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
                 DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
                 DOUT << "2addr:         TO 3-ADDR: " << *New;
-                LV.instructionChanged(mi, New);  // Update live variables
-                mbbi->insert(mi, New);           // Insert the new inst
                 mbbi->erase(mi);                 // Nuke the old inst.
                 mi = New;
                 ++NumConvertedTo3Addr;
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 8f98b51..a795856 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -97,8 +97,7 @@
   }
 
   ModRef MRInfo;
-  if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo,
-                               TargetInstrInfo::TIED_TO)) {
+  if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo, TOI::TIED_TO)) {
     // Folded a two-address operand.
     MRInfo = isModRef;
   } else if (OldMI->getOperand(OpNo).isDef()) {
@@ -592,8 +591,7 @@
         // aren't allowed to modify the reused register.  If none of these cases
         // apply, reuse it.
         bool CanReuse = true;
-        int ti = TII->getOperandConstraint(MI.getOpcode(), i,
-                                           TargetInstrInfo::TIED_TO);
+        int ti = TII->getOperandConstraint(MI.getOpcode(), i, TOI::TIED_TO);
         if (ti != -1 &&
             MI.getOperand(ti).isReg() && 
             MI.getOperand(ti).getReg() == VirtReg) {