commit | ba5dc44b00537fffb5a0fbc36906fff17de1b5af | [log] [tgz] |
---|---|---|
author | Andrew Lenharth <andrewl@lenharth.org> | Wed Jun 29 12:23:34 2005 +0000 |
committer | Andrew Lenharth <andrewl@lenharth.org> | Wed Jun 29 12:23:34 2005 +0000 |
tree | 35a97530be92dd249449264f54d5fbe59bf164db | |
parent | fce587e58b88d1a10921c09acc6951b2e38d76f6 [diff] [blame] |
fix most regressions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22307 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index eef0d84..b4e9493 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1289,7 +1289,8 @@ } if ((DestType == MVT::f64 || DestType == MVT::f32) - && opcode != ISD::CALL && opcode != ISD::TAILCALL) + && opcode != ISD::CALL && opcode != ISD::TAILCALL + && opcode != ISD::CopyFromReg && opcode != ISD::LOAD) return SelectExprFP(N, Result); switch (opcode) {