brg
X86Implicit.cpp, X86Implicit.h: New files.
InstSelectSimple.cpp: Add some clarifications in visitCallInst comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4874 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index d9facda..a601660 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -397,6 +397,8 @@
{
case cByte:
case cShort:
+ // Promote V to 32 bits wide, and move the result into EAX,
+ // then push EAX.
promote32 (X86::EAX, v);
BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
break;
@@ -405,7 +407,7 @@
BuildMI (BB, X86::PUSHr32, 1).addReg (argReg);
break;
default:
- // FIXME
+ // FIXME: long/ulong/double args not handled.
visitInstruction (CI);
break;
}
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index d9facda..a601660 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -397,6 +397,8 @@
{
case cByte:
case cShort:
+ // Promote V to 32 bits wide, and move the result into EAX,
+ // then push EAX.
promote32 (X86::EAX, v);
BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
break;
@@ -405,7 +407,7 @@
BuildMI (BB, X86::PUSHr32, 1).addReg (argReg);
break;
default:
- // FIXME
+ // FIXME: long/ulong/double args not handled.
visitInstruction (CI);
break;
}
diff --git a/lib/Target/X86/X86Implicit.cpp b/lib/Target/X86/X86Implicit.cpp
new file mode 100644
index 0000000..84becd6
--- /dev/null
+++ b/lib/Target/X86/X86Implicit.cpp
@@ -0,0 +1,87 @@
+//===-- X86Implicit.cpp - All the implicit uses and defs for X86 ops ------===//
+//
+// This defines a class which maps X86 opcodes to the registers that they
+// implicitly modify or use.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86Implicit.h"
+#include <map>
+#include <vector>
+
+X86Implicit::X86Implicit ()
+{
+ implicitUses[X86::CBW].push_back (X86::AL);
+ implicitDefs[X86::CBW].push_back (X86::AX);
+
+ implicitUses[X86::CDQ].push_back (X86::EAX);
+ implicitDefs[X86::CDQ].push_back (X86::EDX);
+
+ implicitUses[X86::CWD].push_back (X86::AX);
+ implicitDefs[X86::CWD].push_back (X86::DX);
+
+ implicitUses[X86::DIVrr16].push_back (X86::DX);
+ implicitUses[X86::DIVrr16].push_back (X86::AX);
+ implicitDefs[X86::DIVrr16].push_back (X86::DX);
+ implicitDefs[X86::DIVrr16].push_back (X86::AX);
+
+ implicitUses[X86::DIVrr32].push_back (X86::EDX);
+ implicitUses[X86::DIVrr32].push_back (X86::EAX);
+ implicitDefs[X86::DIVrr32].push_back (X86::EDX);
+ implicitDefs[X86::DIVrr32].push_back (X86::EAX);
+
+ implicitUses[X86::DIVrr8].push_back (X86::AX);
+ implicitDefs[X86::DIVrr8].push_back (X86::AL);
+ implicitDefs[X86::DIVrr8].push_back (X86::AH);
+
+ implicitDefs[X86::FNSTSWr8].push_back (X86::AX);
+
+ implicitUses[X86::IDIVrr16].push_back (X86::DX);
+ implicitUses[X86::IDIVrr16].push_back (X86::AX);
+ implicitDefs[X86::IDIVrr16].push_back (X86::DX);
+ implicitDefs[X86::IDIVrr16].push_back (X86::AX);
+
+ implicitUses[X86::IDIVrr32].push_back (X86::EDX);
+ implicitUses[X86::IDIVrr32].push_back (X86::EAX);
+ implicitDefs[X86::IDIVrr32].push_back (X86::EDX);
+ implicitDefs[X86::IDIVrr32].push_back (X86::EAX);
+
+ implicitUses[X86::IDIVrr8].push_back (X86::AX);
+ implicitDefs[X86::IDIVrr8].push_back (X86::AL);
+ implicitDefs[X86::IDIVrr8].push_back (X86::AH);
+
+ implicitUses[X86::LEAVE].push_back (X86::EBP);
+ implicitDefs[X86::LEAVE].push_back (X86::EBP);
+
+ implicitUses[X86::MULrr16].push_back (X86::AX);
+ implicitDefs[X86::MULrr16].push_back (X86::DX);
+ implicitDefs[X86::MULrr16].push_back (X86::AX);
+
+ implicitUses[X86::MULrr32].push_back (X86::EAX);
+ implicitDefs[X86::MULrr32].push_back (X86::EDX);
+ implicitDefs[X86::MULrr32].push_back (X86::EAX);
+
+ implicitUses[X86::MULrr8].push_back (X86::AL);
+ implicitDefs[X86::MULrr8].push_back (X86::AX);
+
+ implicitUses[X86::SAHF].push_back (X86::AH);
+
+ implicitUses[X86::SARrr16].push_back (X86::CL);
+
+ implicitUses[X86::SARrr32].push_back (X86::CL);
+
+ implicitUses[X86::SARrr8].push_back (X86::CL);
+
+ implicitUses[X86::SHLrr16].push_back (X86::CL);
+
+ implicitUses[X86::SHLrr32].push_back (X86::CL);
+
+ implicitUses[X86::SHLrr8].push_back (X86::CL);
+
+ implicitUses[X86::SHRrr16].push_back (X86::CL);
+
+ implicitUses[X86::SHRrr32].push_back (X86::CL);
+
+ implicitUses[X86::SHRrr8].push_back (X86::CL);
+}
+
diff --git a/lib/Target/X86/X86Implicit.h b/lib/Target/X86/X86Implicit.h
new file mode 100644
index 0000000..c8b8c57
--- /dev/null
+++ b/lib/Target/X86/X86Implicit.h
@@ -0,0 +1,18 @@
+//===-- X86Implicit.h - All the implicit uses and defs for X86 ops --------===//
+//
+// This defines a class which maps X86 opcodes to the registers that they
+// implicitly modify or use.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include <map>
+#include <vector>
+
+class X86Implicit {
+public:
+ typedef std::map <X86::Opcode, std::vector <X86::Register> > ImplicitMap;
+ ImplicitMap implicitUses;
+ ImplicitMap implicitDefs;
+ X86Implicit ();
+};