Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 5b20676..cafd3f2 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -138,10 +138,13 @@
/// operand requires relocation, record the relocation and return zero.
unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO) const {
- if (MO.isReg())
+ if (MO.isReg()) {
return getARMRegisterNumbering(MO.getReg());
- else if (MO.isImm()) {
+ } else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
+ } else if (MO.isFPImm()) {
+ return static_cast<unsigned>(APFloat(MO.getFPImm())
+ .bitcastToAPInt().getHiBits(32).getLimitedValue());
} else {
#ifndef NDEBUG
errs() << MO;
@@ -151,7 +154,6 @@
return 0;
}
-
unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
unsigned OpIdx) const {
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg