diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index aedd7c9..727f0a5 100644
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -414,7 +414,7 @@
     const TargetInstrDesc &TID = I->getDesc();
     if (TID.isCall())
       Time += 10;
-    else if (TID.isSimpleLoad() || TID.mayStore())
+    else if (TID.mayLoad() || TID.mayStore())
       Time += 2;
     else
       ++Time;
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index b85daa1..cd5f321 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -834,7 +834,7 @@
   assert(Offset && "This code isn't needed if offset already handled!");
 
   if (isThumb) {
-    if (Desc.isSimpleLoad()) {
+    if (Desc.mayLoad()) {
       // Use the destination register to materialize sp + offset.
       unsigned TmpReg = MI.getOperand(0).getReg();
       bool UseRR = false;
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index c4e6edc..531b7fa 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -570,7 +570,9 @@
 
 
 //load address, rellocated gpdist form
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
+    mayLoad = 1 in {
 def LDAg  : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
 }
@@ -589,7 +591,9 @@
 def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
 def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
 }
-let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
+let OutOperandList = (ops GPRC:$RA),
+    InOperandList = (ops s64imm:$DISP, GPRC:$RB),
+    mayLoad = 1 in {
 def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
 def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
 }
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index b9b7496..14745e6 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -72,7 +72,7 @@
   
   const TargetInstrDesc &TID = TII.get(Opcode);
   
-  isLoad  = TID.isSimpleLoad();
+  isLoad  = TID.mayLoad();
   isStore = TID.mayStore();
   
   unsigned TSFlags = TID.TSFlags;
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 6867cd7..a2f1834 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -487,6 +487,7 @@
                    PPC970_DGroup_Cracked;
 
 // Update forms.
+let mayLoad = 1 in
 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
                             ptr_rc:$rA),
                     "lhau $rD, $disp($rA)", LdStGeneral,
@@ -520,6 +521,7 @@
                    
                    
 // Update forms.
+let mayLoad = 1 in {
 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                     "lbzu $rD, $addr", LdStGeneral,
                     []>, RegConstraint<"$addr.reg = $ea_result">,
@@ -533,6 +535,7 @@
                     []>, RegConstraint<"$addr.reg = $ea_result">,
                     NoEncode<"$ea_result">;
 }
+}
 
 
 // Full 8-byte loads.
@@ -544,6 +547,7 @@
                    "ldx $rD, $src", LdStLD,
                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
                    
+let mayLoad = 1 in
 def LDU  : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
                     "ldu $rD, $addr", LdStLD,
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 0cb7c85..4106c45 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -683,6 +683,7 @@
 
 
 // Unindexed (r+i) Loads with Update (preinc).
+let mayLoad = 1 in {
 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
                    "lbzu $rD, $addr", LdStGeneral,
                    []>, RegConstraint<"$addr.reg = $ea_result">,
@@ -713,6 +714,7 @@
                   []>, RegConstraint<"$addr.reg = $ea_result">,
                    NoEncode<"$ea_result">;
 }
+}
 
 // Indexed (r+r) Loads.
 //
diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp
index 859a8cc..b3ed27b 100644
--- a/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1759,6 +1759,15 @@
     MayLoad = true;
   }
 
+  // Sanity-check the isSimpleLoad flag.
+  if (Inst.isSimpleLoad) {
+    if (!MayLoad)
+      fprintf(stderr,
+              "Warning: mayLoad flag not set or inferred for instruction '%s'"
+              " which has isSimpleLoad set.\n",
+              Inst.TheDef->getName().c_str());
+  }
+
   if (Inst.neverHasSideEffects) {
     if (HadPattern)
       fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp
index 3674a13..a6e3730 100644
--- a/utils/TableGen/DAGISelEmitter.cpp
+++ b/utils/TableGen/DAGISelEmitter.cpp
@@ -1097,7 +1097,7 @@
 
       // Generate MemOperandSDNodes nodes for each memory accesses covered by 
       // this pattern.
-      if (II.isSimpleLoad | II.mayLoad | II.mayStore) {
+      if (II.mayLoad | II.mayStore) {
         std::vector<std::string>::const_iterator mi, mie;
         for (mi = LSI.begin(), mie = LSI.end(); mi != mie; ++mi) {
           std::string LSIName = "LSI_" + *mi;