Fixed a bug when trying to optimize a extract vector element of a
bit convert that changes the number of elements of a shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60829 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index aae4c59..9cc8061 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4874,7 +4874,8 @@
MVT LVT = EVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
MVT BCVT = InVec.getOperand(0).getValueType();
- if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
+ if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()) ||
+ VT.getVectorNumElements() != BCVT.getVectorNumElements())
return SDValue();
InVec = InVec.getOperand(0);
EVT = BCVT.getVectorElementType();
diff --git a/test/CodeGen/X86/extractelement-shuffle.ll b/test/CodeGen/X86/extractelement-shuffle.ll
new file mode 100644
index 0000000..b00c8e4
--- /dev/null
+++ b/test/CodeGen/X86/extractelement-shuffle.ll
@@ -0,0 +1,13 @@
+; RUN: llvm-as < %s | llc
+
+; Examples that exhibits a bug in DAGCombine. The case is triggered by the
+; following program. The bug is DAGCombine assumes that the bit convert
+; preserves the number of elements so the optimization code tries to read
+; through the 3rd mask element, which doesn't exist.
+define i32 @update(<2 x i64> %val1, <2 x i64> %val2) nounwind readnone {
+entry:
+ %shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>;
+ %bit = bitcast <2 x i64> %shuf to <4 x i32>;
+ %res = extractelement <4 x i32> %bit, i32 3;
+ ret i32 %res;
+}
\ No newline at end of file