diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index f113b16..0098a42 100644
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -17,7 +17,6 @@
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Transforms/Scalar.h"
-#include <iostream>
 using namespace llvm;
 
 bool LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
@@ -46,18 +45,18 @@
   
   // Print the instruction selected machine code...
   if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
   if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
@@ -71,11 +70,11 @@
   PM.add(createDebugLabelFoldingPass());
   
   if (PrintMachineCode)  // Print the register-allocated code
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   switch (FileType) {
@@ -127,32 +126,32 @@
   
   // Print the instruction selected machine code...
   if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   // Perform register allocation to convert to a concrete x86 representation
   PM.add(createRegisterAllocator());
   
   if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   PM.add(createPrologEpilogCodeInserter());
   
   if (PrintMachineCode)  // Print the register-allocated code
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   // Branch folding must be run after regalloc and prolog/epilog insertion.
   if (!Fast)
     PM.add(createBranchFoldingPass());
   
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+    PM.add(createMachineFunctionPrinterPass(cerr.stream()));
   
   
   addCodeEmitter(PM, Fast, MCE);
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index f5c81da..e0713c8 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -35,27 +35,26 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Config/alloca.h"
 #include <algorithm>
-#include <iostream>
 using namespace llvm;
 
 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
 
 void LiveVariables::VarInfo::dump() const {
-  std::cerr << "Register Defined by: ";
+  cerr << "Register Defined by: ";
   if (DefInst) 
-    std::cerr << *DefInst;
+    cerr << *DefInst;
   else
-    std::cerr << "<null>\n";
-  std::cerr << "  Alive in blocks: ";
+    cerr << "<null>\n";
+  cerr << "  Alive in blocks: ";
   for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
-    if (AliveBlocks[i]) std::cerr << i << ", ";
-  std::cerr << "\n  Killed by:";
+    if (AliveBlocks[i]) cerr << i << ", ";
+  cerr << "\n  Killed by:";
   if (Kills.empty())
-    std::cerr << " No instructions.\n";
+    cerr << " No instructions.\n";
   else {
     for (unsigned i = 0, e = Kills.size(); i != e; ++i)
-      std::cerr << "\n    #" << i << ": " << *Kills[i];
-    std::cerr << "\n";
+      cerr << "\n    #" << i << ": " << *Kills[i];
+    cerr << "\n";
   }
 }
 
diff --git a/lib/CodeGen/MachOWriter.cpp b/lib/CodeGen/MachOWriter.cpp
index 7c0855a..3906769 100644
--- a/lib/CodeGen/MachOWriter.cpp
+++ b/lib/CodeGen/MachOWriter.cpp
@@ -32,7 +32,6 @@
 #include "llvm/Support/Mangler.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
-#include <iostream>
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp
index 8d8e9b7..a626f4f 100644
--- a/lib/CodeGen/MachineBasicBlock.cpp
+++ b/lib/CodeGen/MachineBasicBlock.cpp
@@ -19,7 +19,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/LeakDetector.h"
-#include <iostream>
 #include <algorithm>
 using namespace llvm;
 
@@ -87,7 +86,7 @@
 }
 
 void MachineBasicBlock::dump() const {
-  print(std::cerr);
+  print(*cerr.stream());
 }
 
 void MachineBasicBlock::print(std::ostream &OS) const {
diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 5d82f72..5aaae6d 100644
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -31,9 +31,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Config/config.h"
 #include <fstream>
-#include <iostream>
 #include <sstream>
-
 using namespace llvm;
 
 static AnnotationID MF_AID(
@@ -177,7 +175,7 @@
 }
 
 
-void MachineFunction::dump() const { print(std::cerr); }
+void MachineFunction::dump() const { print(*cerr.stream()); }
 
 void MachineFunction::print(std::ostream &OS) const {
   OS << "# Machine code for " << Fn->getName () << "():\n";
@@ -268,8 +266,8 @@
 #ifndef NDEBUG
   ViewGraph(this, "mf" + getFunction()->getName());
 #else
-  std::cerr << "SelectionDAG::viewGraph is only available in debug builds on "
-            << "systems with Graphviz or gv!\n";
+  cerr << "SelectionDAG::viewGraph is only available in debug builds on "
+       << "systems with Graphviz or gv!\n";
 #endif // NDEBUG
 }
 
@@ -350,7 +348,7 @@
 }
 
 void MachineFrameInfo::dump(const MachineFunction &MF) const {
-  print(MF, std::cerr);
+  print(MF, *cerr.stream());
 }
 
 
@@ -390,7 +388,7 @@
   return TD->getPointerAlignment(); 
 }
 
-void MachineJumpTableInfo::dump() const { print(std::cerr); }
+void MachineJumpTableInfo::dump() const { print(*cerr.stream()); }
 
 
 //===----------------------------------------------------------------------===//
@@ -473,4 +471,4 @@
   }
 }
 
-void MachineConstantPool::dump() const { print(std::cerr); }
+void MachineConstantPool::dump() const { print(*cerr.stream()); }
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 262f8c2..87ef003 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -27,7 +27,6 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -192,7 +191,7 @@
         unsigned virtualReg = (unsigned) op.getReg();
         DOUT << "op: " << op << "\n";
         DOUT << "\t inst[" << i << "]: ";
-        DEBUG(MI->print(std::cerr, TM));
+        DEBUG(MI->print(*cerr.stream(), TM));
 
         // make sure the same virtual register maps to the same physical
         // register in any given instruction
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c279982..5f92df3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -26,7 +26,6 @@
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
-#include <iostream>
 #include <set>
 #include <algorithm>
 #include <cmath>
@@ -2887,7 +2886,7 @@
              dyn_cast<GlobalAddressSDNode>(this)) {
     int offset = GADN->getOffset();
     cerr << "<";
-    WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
+    WriteAsOperand(*cerr.stream(), GADN->getGlobal()) << ">";
     if (offset > 0)
       cerr << " + " << offset;
     else
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 932542d..be19e46 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -41,7 +41,6 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -102,7 +101,7 @@
 
         if (FirstTied) {
           ++NumTwoAddressInstrs;
-          DOUT << '\t'; DEBUG(mi->print(std::cerr, &TM));
+          DOUT << '\t'; DEBUG(mi->print(*cerr.stream(), &TM));
         }
         FirstTied = false;
 
@@ -195,7 +194,7 @@
           MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
 
           MachineBasicBlock::iterator prevMi = prior(mi);
-          DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(std::cerr, &TM));
+          DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
 
           // Update live variables for regA
           LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
@@ -220,7 +219,7 @@
         mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
         MadeChange = true;
 
-        DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(std::cerr, &TM));
+        DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(*cerr.stream(), &TM));
       }
     }
   }