Eliminate the distinction between "real" and "unreal" instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11986 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index a9139d4..815a2d9 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -83,27 +83,25 @@
///
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned descSize; // number of entries in the desc array
+ unsigned NumOpcodes; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant: All instruction sets use opcode #0 as the PHI instruction
enum { PHI = 0 };
- unsigned getNumRealOpCodes() const { return numRealOpCodes; }
- unsigned getNumTotalOpCodes() const { return descSize; }
+ unsigned getNumOpcodes() const { return NumOpcodes; }
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const TargetInstrDescriptor& get(MachineOpCode opCode) const {
- assert(opCode >= 0 && opCode < (int)descSize);
+ assert((unsigned)opCode < NumOpcodes);
return desc[opCode];
}
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index b273bcb..5395a81 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -520,7 +520,7 @@
nextEarliestIssueTime(0),
choicesForSlot(nslots),
numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
- nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
+ nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(),
(cycles_t) 0) // set all to 0
{
updateTime(0);
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index b273bcb..5395a81 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -520,7 +520,7 @@
nextEarliestIssueTime(0),
choicesForSlot(nslots),
numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
- nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
+ nextEarliestStartTime(target.getInstrInfo().getNumOpcodes(),
(cycles_t) 0) // set all to 0
{
updateTime(0);
diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp
index f33223c..33538ce 100644
--- a/lib/Target/TargetSchedInfo.cpp
+++ b/lib/Target/TargetSchedInfo.cpp
@@ -119,7 +119,7 @@
TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>&
instrRUForClasses)
{
- int numOpCodes = mii->getNumRealOpCodes();
+ int numOpCodes = mii->getNumOpcodes();
instrRUsages.resize(numOpCodes);
// First get the resource usage information from the class resource usages.
@@ -149,7 +149,7 @@
TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>&
instrRUForClasses)
{
- int numOpCodes = mii->getNumRealOpCodes();
+ int numOpCodes = mii->getNumOpcodes();
issueGaps.resize(numOpCodes);
conflictLists.resize(numOpCodes);