commit bcecf33dc23c513d0919af22f5f856da36039feb
author Evan Cheng <evan.cheng@apple.com> Sat Dec 17 01:19:28 2005 +0000
committer Evan Cheng <evan.cheng@apple.com> Sat Dec 17 01:19:28 2005 +0000
tree 12004223ff9c34d59abec68f0b4ec10789ae5b9e
parent 5610219c07ad24dcd861b829b39b0b1fdfb6a48e

Support for read / write from explicit registers with FlagVT type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenTarget.cpp

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index b16bc88..c06b73f 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -45,6 +45,7 @@
   case MVT::f64:   return "f64";
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
+  case MVT::Flag:  return "Flag";
   case MVT::isVoid:return "void";
   case MVT::v16i8: return "v16i8";
   case MVT::v8i16: return "v8i16";
@@ -69,6 +70,7 @@
   case MVT::f64:   return "f64";
   case MVT::f80:   return "f80";
   case MVT::f128:  return "f128";
+  case MVT::Flag:  return "Flag";
   case MVT::isVoid:return "isVoid";
   case MVT::v16i8: return "v16i8";
   case MVT::v8i16: return "v8i16";