llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
index 77e66c8..bc4facd 100644
--- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
@@ -265,7 +265,7 @@
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
@@ -276,7 +276,7 @@
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
- LLVM_UNREACHABLE("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
+ llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
@@ -434,7 +434,7 @@
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index ddb9a36..8f704ec 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -378,7 +378,7 @@
break;
case 'v': // not offsetable
#if 1
- LLVM_UNREACHABLE("InlineAsmMemoryOperand 'v' constraint not handled.");
+ llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
#else
SelectAddrIdxOnly(Op, Op, Op0, Op1);
#endif
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 6b9df67..2042a93 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -875,7 +875,7 @@
}
}
- LLVM_UNREACHABLE("LowerConstantPool: Relocation model other than static"
+ llvm_unreachable("LowerConstantPool: Relocation model other than static"
" not supported.");
return SDValue();
}
@@ -906,7 +906,7 @@
}
}
- LLVM_UNREACHABLE("LowerJumpTable: Relocation model other than static"
+ llvm_unreachable("LowerJumpTable: Relocation model other than static"
" not supported.");
return SDValue();
}
@@ -1138,7 +1138,7 @@
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
switch (Arg.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
+ default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i8:
case MVT::i16:
case MVT::i32:
@@ -1270,7 +1270,7 @@
// If the call has results, copy the values out of the ret val registers.
switch (TheCall->getValueType(0).getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ret value!");
+ default: llvm_unreachable("Unexpected ret value!");
case MVT::Other: break;
case MVT::i32:
if (TheCall->getValueType(1) == MVT::i32) {
@@ -1738,7 +1738,7 @@
} else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
V2EltIdx0 = 2;
} else
- LLVM_UNREACHABLE("Unhandled vector type in LowerVECTOR_SHUFFLE");
+ llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
for (unsigned i = 0; i != MaxElts; ++i) {
if (SVN->getMaskElt(i) < 0)
@@ -1834,7 +1834,7 @@
// Create a constant vector:
switch (Op.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected constant value type in "
+ default: llvm_unreachable("Unexpected constant value type in "
"LowerSCALAR_TO_VECTOR");
case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
@@ -1853,7 +1853,7 @@
} else {
// Otherwise, copy the value from one register to another:
switch (Op0.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected value type in LowerSCALAR_TO_VECTOR");
+ default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
case MVT::i8:
case MVT::i16:
case MVT::i32:
@@ -1880,13 +1880,13 @@
// sanity checks:
if (VT == MVT::i8 && EltNo >= 16)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
else if (VT == MVT::i16 && EltNo >= 8)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
else if (VT == MVT::i32 && EltNo >= 4)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
else if (VT == MVT::i64 && EltNo >= 2)
- LLVM_UNREACHABLE("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
+ llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
// i32 and i64: Element 0 is the preferred slot
@@ -2065,7 +2065,7 @@
assert(Op.getValueType() == MVT::i8);
switch (Opc) {
default:
- LLVM_UNREACHABLE("Unhandled i8 math operator");
+ llvm_unreachable("Unhandled i8 math operator");
/*NOTREACHED*/
break;
case ISD::ADD: {
@@ -2585,7 +2585,7 @@
cerr << "*Op.getNode():\n";
Op.getNode()->dump();
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
case ISD::LOAD:
case ISD::EXTLOAD:
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index eba1ca1..26a4241 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -314,7 +314,7 @@
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -347,7 +347,7 @@
} else if (RC == SPU::VECREGRegisterClass) {
/* Opc = PPC::STVX; */
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
@@ -383,7 +383,7 @@
} else if (RC == SPU::VECREGRegisterClass) {
opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
} else {
- LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!");
+ llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -420,7 +420,7 @@
} else if (RC == SPU::GPRCRegisterClass) {
/* Opc = something else! */
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);