llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
index cec3273..fddc1c2 100644
--- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
@@ -71,7 +71,7 @@
unsigned enumRegToMachineReg(unsigned enumReg) {
switch (enumReg) {
- default: LLVM_UNREACHABLE("Unhandled register!");
+ default: llvm_unreachable("Unhandled register!");
case PPC::CR0: return 0;
case PPC::CR1: return 1;
case PPC::CR2: return 2;
@@ -81,7 +81,7 @@
case PPC::CR6: return 6;
case PPC::CR7: return 7;
}
- llvm_unreachable();
+ llvm_unreachable(0);
}
/// printInstruction - This method is automatically generated by tablegen
@@ -349,7 +349,7 @@
void PPCAsmPrinter::printOp(const MachineOperand &MO) {
switch (MO.getType()) {
case MachineOperand::MO_Immediate:
- LLVM_UNREACHABLE("printOp() does not handle immediate values");
+ llvm_unreachable("printOp() does not handle immediate values");
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMBB());
@@ -551,7 +551,7 @@
if (printInstruction(MI))
return; // Printer was automatically generated
- LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
+ llvm_unreachable("Unhandled instruction in asm writer!");
}
/// runOnMachineFunction - This uses the printMachineInstruction()
@@ -571,7 +571,7 @@
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
@@ -706,7 +706,7 @@
case GlobalValue::PrivateLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
@@ -748,7 +748,7 @@
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage: // Symbols default to internal.
break;
@@ -936,7 +936,7 @@
case GlobalValue::PrivateLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 4943e5c..4090a22 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -181,7 +181,7 @@
assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
}
switch (MI.getOpcode()) {
- default: MI.dump(); LLVM_UNREACHABLE("Unknown instruction for relocation!");
+ default: MI.dump(); llvm_unreachable("Unknown instruction for relocation!");
case PPC::LIS:
case PPC::LIS8:
case PPC::ADDIS:
@@ -268,7 +268,7 @@
#ifndef NDEBUG
cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
return rv;
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 244d395..e754d9d 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -142,7 +142,7 @@
return Hazard;
switch (InstrType) {
- default: LLVM_UNREACHABLE("Unknown instruction type!");
+ default: llvm_unreachable("Unknown instruction type!");
case PPCII::PPC970_FXU:
case PPCII::PPC970_LSU:
case PPCII::PPC970_FPU:
@@ -168,7 +168,7 @@
if (isLoad && NumStores) {
unsigned LoadSize;
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown load!");
+ default: llvm_unreachable("Unknown load!");
case PPC::LBZ: case PPC::LBZU:
case PPC::LBZX:
case PPC::LBZ8: case PPC::LBZU8:
@@ -236,7 +236,7 @@
if (isStore) {
unsigned ThisStoreSize;
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown store instruction!");
+ default: llvm_unreachable("Unknown store instruction!");
case PPC::STB: case PPC::STB8:
case PPC::STBU: case PPC::STBU8:
case PPC::STBX: case PPC::STBX8:
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index b17e54d..9221355 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -602,8 +602,8 @@
case ISD::SETONE:
case ISD::SETOLE:
case ISD::SETOGE:
- LLVM_UNREACHABLE("Should be lowered by legalize!");
- default: LLVM_UNREACHABLE("Unknown condition!");
+ llvm_unreachable("Should be lowered by legalize!");
+ default: llvm_unreachable("Unknown condition!");
case ISD::SETOEQ:
case ISD::SETEQ: return PPC::PRED_EQ;
case ISD::SETUNE:
@@ -634,7 +634,7 @@
Invert = false;
Other = -1;
switch (CC) {
- default: LLVM_UNREACHABLE("Unknown condition!");
+ default: llvm_unreachable("Unknown condition!");
case ISD::SETOLT:
case ISD::SETLT: return 0; // Bit #0 = SETOLT
case ISD::SETOGT:
@@ -653,7 +653,7 @@
case ISD::SETOGE:
case ISD::SETOLE:
case ISD::SETONE:
- LLVM_UNREACHABLE("Invalid branch code: should be expanded by legalize");
+ llvm_unreachable("Invalid branch code: should be expanded by legalize");
// These are invalid for floating point. Assume integer.
case ISD::SETULT: return 0;
case ISD::SETUGT: return 1;
@@ -941,7 +941,7 @@
// Handle PPC32 integer and normal FP loads.
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid PPC load type!");
+ default: llvm_unreachable("Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
case MVT::f32: Opcode = PPC::LFSU; break;
case MVT::i32: Opcode = PPC::LWZU; break;
@@ -953,7 +953,7 @@
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid PPC load type!");
+ default: llvm_unreachable("Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;
case MVT::i32: Opcode = PPC::LWZU8; break;
case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
@@ -970,7 +970,7 @@
PPCLowering.getPointerTy(),
MVT::Other, Ops, 3);
} else {
- LLVM_UNREACHABLE("R+R preindex loads not supported yet!");
+ llvm_unreachable("R+R preindex loads not supported yet!");
}
}
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 842361f..5cabf04 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1156,7 +1156,7 @@
SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) {
- LLVM_UNREACHABLE("TLS not implemented for PPC.");
+ llvm_unreachable("TLS not implemented for PPC.");
return SDValue(); // Not reached
}
@@ -1251,7 +1251,7 @@
unsigned VarArgsNumFPR,
const PPCSubtarget &Subtarget) {
- LLVM_UNREACHABLE("VAARG not yet implemented for the SVR4 ABI!");
+ llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
return SDValue(); // Not reached
}
@@ -1544,7 +1544,7 @@
switch (ValVT.getSimpleVT()) {
default:
- LLVM_UNREACHABLE("ValVT not supported by FORMAL_ARGUMENTS Lowering");
+ llvm_unreachable("ValVT not supported by FORMAL_ARGUMENTS Lowering");
case MVT::i32:
RC = PPC::GPRCRegisterClass;
break;
@@ -1785,7 +1785,7 @@
}
switch(ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i32:
case MVT::f32:
VecArgOffset += isPPC64 ? 8 : 4;
@@ -1892,7 +1892,7 @@
}
switch (ObjectVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled argument type!");
+ default: llvm_unreachable("Unhandled argument type!");
case MVT::i32:
if (!isPPC64) {
if (GPR_idx != Num_GPR_Regs) {
@@ -2591,7 +2591,7 @@
cerr << "Call operand #" << i << " has unhandled type "
<< ArgVT.getMVTString() << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
} else {
@@ -2902,7 +2902,7 @@
}
switch (Arg.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
+ default: llvm_unreachable("Unexpected ValueType for argument!");
case MVT::i32:
case MVT::i64:
if (GPR_idx != NumGPRs) {
@@ -3309,7 +3309,7 @@
SDValue Tmp;
switch (Op.getValueType().getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unhandled FP_TO_INT type in custom expander!");
+ default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
case MVT::i32:
Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
PPCISD::FCTIDZ,
@@ -3795,7 +3795,7 @@
int ShufIdxs[16];
switch (OpNum) {
- default: LLVM_UNREACHABLE("Unknown i32 permute!");
+ default: llvm_unreachable("Unknown i32 permute!");
case OP_VMRGHW:
ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
@@ -4147,7 +4147,7 @@
}
return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
} else {
- LLVM_UNREACHABLE("Unknown mul to lower!");
+ llvm_unreachable("Unknown mul to lower!");
}
}
@@ -4155,7 +4155,7 @@
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!");
+ default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
@@ -4817,7 +4817,7 @@
BB = exitMBB;
BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
} else {
- LLVM_UNREACHABLE("Unexpected instr type to insert");
+ llvm_unreachable("Unexpected instr type to insert");
}
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
@@ -5192,7 +5192,7 @@
if (!CST) return; // Must be an immediate to match.
unsigned Value = CST->getZExtValue();
switch (Letter) {
- default: LLVM_UNREACHABLE("Unknown constraint letter!");
+ default: llvm_unreachable("Unknown constraint letter!");
case 'I': // "I" is a signed 16-bit constant.
if ((short)Value == (int)Value)
Result = DAG.getTargetConstant(Value, Op.getValueType());
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 63adf32..8b5e4b2 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -487,7 +487,7 @@
.addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
return false;
@@ -538,7 +538,7 @@
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::STVX;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, getKillRegState(isKill));
@@ -634,7 +634,7 @@
NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
}
@@ -676,7 +676,7 @@
} else if (RC == PPC::VRRCRegisterClass) {
Opc = PPC::LVX;
} else {
- LLVM_UNREACHABLE("Unknown regclass!");
+ llvm_unreachable("Unknown regclass!");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index 91deca1..ef25d92 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -199,7 +199,7 @@
);
#else
void PPC32CompilationCallback() {
- LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
+ llvm_unreachable("This is not a power pc, you can't execute this!");
}
#endif
@@ -265,7 +265,7 @@
);
#else
void PPC64CompilationCallback() {
- LLVM_UNREACHABLE("This is not a power pc, you can't execute this!");
+ llvm_unreachable("This is not a power pc, you can't execute this!");
}
#endif
@@ -383,7 +383,7 @@
unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
switch ((PPC::RelocationType)MR->getRelocationType()) {
- default: LLVM_UNREACHABLE("Unknown relocation type!");
+ default: llvm_unreachable("Unknown relocation type!");
case PPC::reloc_pcrel_bx:
// PC-relative relocation for b and bl instructions.
ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
index 9e57bd9..4c14454 100644
--- a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
+++ b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
@@ -47,9 +47,9 @@
Addr = (uintptr_t)MR.getResultPointer() + ToAddr;
switch ((PPC::RelocationType)MR.getRelocationType()) {
- default: LLVM_UNREACHABLE("Unknown PPC relocation type!");
+ default: llvm_unreachable("Unknown PPC relocation type!");
case PPC::reloc_absolute_low_ix:
- LLVM_UNREACHABLE("Unhandled PPC relocation type!");
+ llvm_unreachable("Unhandled PPC relocation type!");
break;
case PPC::reloc_vanilla:
{
diff --git a/lib/Target/PowerPC/PPCPredicates.cpp b/lib/Target/PowerPC/PPCPredicates.cpp
index bb9e166..12bb0a1 100644
--- a/lib/Target/PowerPC/PPCPredicates.cpp
+++ b/lib/Target/PowerPC/PPCPredicates.cpp
@@ -18,7 +18,7 @@
PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
switch (Opcode) {
- default: LLVM_UNREACHABLE("Unknown PPC branch opcode!");
+ default: llvm_unreachable("Unknown PPC branch opcode!");
case PPC::PRED_EQ: return PPC::PRED_NE;
case PPC::PRED_NE: return PPC::PRED_EQ;
case PPC::PRED_LT: return PPC::PRED_GE;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 6f807fe..6016eb4 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -113,7 +113,7 @@
case R30: case X30: case F30: case V30: case CR7EQ: return 30;
case R31: case X31: case F31: case V31: case CR7UN: return 31;
default:
- LLVM_UNREACHABLE("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
+ llvm_unreachable("Unhandled reg in PPCRegisterInfo::getRegisterNumbering!");
}
}
@@ -1065,7 +1065,7 @@
MinVR = Reg;
}
} else {
- LLVM_UNREACHABLE("Unknown RegisterClass!");
+ llvm_unreachable("Unknown RegisterClass!");
}
}