commit bdc9869dbfa40579236405db73897a9fd19d1ed0
author Evan Cheng <evan.cheng@apple.com> Thu May 03 23:30:36 2007 +0000
committer Evan Cheng <evan.cheng@apple.com> Thu May 03 23:30:36 2007 +0000
tree d63f750bd3635df037366d7165551fc93a4d3398
parent 2acc7601650654d03cd53faeece8d7685a203105

Should never see an indexed load / store with zero offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMAsmPrinter.cpp

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index c35ef57..9454fb7 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -433,10 +433,11 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
 
   if (!MO1.getReg()) {
-    if (ARM_AM::getAM2Offset(MO2.getImm()))  // Don't print +0.
-      O << "#"
-        << (char)ARM_AM::getAM2Op(MO2.getImm())
-        << ARM_AM::getAM2Offset(MO2.getImm());
+    unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
+    assert(ImmOffs && "Malformed indexed load / store!");
+    O << "#"
+      << (char)ARM_AM::getAM2Op(MO2.getImm())
+      << ImmOffs;
     return;
   }
 
@@ -483,8 +484,9 @@
   }
 
   unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
+  assert(ImmOffs && "Malformed indexed load / store!");
   O << "#"
-  << (char)ARM_AM::getAM3Op(MO2.getImm())
+    << (char)ARM_AM::getAM3Op(MO2.getImm())
     << ImmOffs;
 }