Add nodes & dummy matchers for some v{zip,uzp,trn} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79622 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 3ef15a1..3b394b0 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1415,6 +1415,36 @@
N->getOperand(4), N->getOperand(5), Chain };
return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
}
+ case ARMISD::VZIP16: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VZIPd16, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VZIP32: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VZIPq32, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VUZP16: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VUZPd16, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VUZP32: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VUZPq32, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VTRN16: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VTRNd16, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
+ case ARMISD::VTRN32: {
+ EVT VT = N->getValueType(0);
+ return CurDAG->getTargetNode(ARM::VTRNq32, dl, VT, VT,
+ N->getOperand(0), N->getOperand(1));
+ }
}
return SelectCode(Op);
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index c55b7b4..2f194d3 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -492,6 +492,15 @@
case ARMISD::VREV64: return "ARMISD::VREV64";
case ARMISD::VREV32: return "ARMISD::VREV32";
case ARMISD::VREV16: return "ARMISD::VREV16";
+ case ARMISD::VZIP32: return "ARMISD::VZIP32";
+ case ARMISD::VZIP16: return "ARMISD::VZIP16";
+ case ARMISD::VZIP8: return "ARMISD::VZIP8";
+ case ARMISD::VUZP32: return "ARMISD::VUZP32";
+ case ARMISD::VUZP16: return "ARMISD::VUZP16";
+ case ARMISD::VUZP8: return "ARMISD::VUZP8";
+ case ARMISD::VTRN32: return "ARMISD::VTRN32";
+ case ARMISD::VTRN16: return "ARMISD::VTRN16";
+ case ARMISD::VTRN8: return "ARMISD::VTRN8";
}
}
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 00e6c8a..b893c58 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -109,6 +109,18 @@
def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
+def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
+ SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
+def NEONzip32 : SDNode<"ARMISD::VZIP32", SDTARMVSHUF2>;
+def NEONzip16 : SDNode<"ARMISD::VZIP16", SDTARMVSHUF2>;
+def NEONzip8 : SDNode<"ARMISD::VZIP8", SDTARMVSHUF2>;
+def NEONuzp32 : SDNode<"ARMISD::VUZP32", SDTARMVSHUF2>;
+def NEONuzp16 : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
+def NEONuzp8 : SDNode<"ARMISD::VUZP16", SDTARMVSHUF2>;
+def NEONtrn32 : SDNode<"ARMISD::VTRN32", SDTARMVSHUF2>;
+def NEONtrn16 : SDNode<"ARMISD::VTRN16", SDTARMVSHUF2>;
+def NEONtrn8 : SDNode<"ARMISD::VTRN8", SDTARMVSHUF2>;
+
//===----------------------------------------------------------------------===//
// NEON operand definitions
//===----------------------------------------------------------------------===//