commit be3034c28893617d31e9ce7ed9ad2e128e92877b
author Evan Cheng <evan.cheng@apple.com> Sat Sep 13 01:38:29 2008 +0000
committer Evan Cheng <evan.cheng@apple.com> Sat Sep 13 01:38:29 2008 +0000
tree 8fbb86f6c08df6ed009fa64da9a03ecab510d342
parent 05fc9664018f867b2184589e8a04cc8f056cfa16

Rely on instruction format to determine so_reg operand for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56181 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMCodeEmitter.cpp

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 7abb7d2..1484d16 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -372,7 +372,11 @@
   }
 
   // Encode shifter operand.
-  if (TID.getNumOperands() - OpIdx > 1)
+  bool HasSoReg = (Format == ARMII::DPRdSoReg ||
+                   Format == ARMII::DPRnSoReg ||
+                   Format == ARMII::DPRSoReg  ||
+                   Format == ARMII::DPRSoRegS);
+  if (HasSoReg)
     // Encode SoReg.
     return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);