commit bf417a6d46d6e1e09fd10e20e863d451924bf083
author Misha Brukman <brukman+llvm@gmail.com> Tue Jul 20 20:43:05 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Tue Jul 20 20:43:05 2004 +0000
tree e621880a2a909c26c4b669817e5c4c258304ef83
parent 1d3a8b0bd88f4a3bc4359c2bf18eda4c62c6b2b2

Treat external variables similarly to those with weak linkage: load indirect.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15047 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 8605380..8c212dc 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -524,9 +524,8 @@
     // GV is located at PC + distance
     unsigned CurPC = makeAnotherReg(Type::IntTy);
     unsigned TmpReg = makeAnotherReg(GV->getType());
-    unsigned Opcode = GV->hasWeakLinkage() ? 
-      PPC32::LOADLoIndirect : 
-      PPC32::LOADLoDirect;
+    unsigned Opcode = (GV->hasWeakLinkage() || GV->isExternal()) ? 
+      PPC32::LOADLoIndirect : PPC32::LOADLoDirect;
       
     // Move PC to destination reg
     BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
@@ -2481,7 +2480,8 @@
       unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
       BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
       BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
-      BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
+      BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg)
+        .addReg(SrcReg2);
       break;
     }
     case cFP32: