Add a subtarget feature for the stfiwx instruction. I know the G5 has it,
but I don't know what other PPC impls do. If someone could update the proc
table, I would appreciate it :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26421 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index 8b9e3a7..272f6d6 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -29,6 +29,8 @@
"Enable GPUL instructions">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction">;
+def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
+ "Enable the stfiwx instruction">;
//===----------------------------------------------------------------------===//
// Register File Description
@@ -58,10 +60,10 @@
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"g5", G5Itineraries,
- [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
+ [FeatureAltivec, FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Feature64Bit /*, Feature64BitRegs */]>;