commit bf9716b9c48d3b0370c715cd79540945f73dc296
author Chris Lattner <sabre@nondot.org> Fri Sep 30 01:29:00 2005 +0000
committer Chris Lattner <sabre@nondot.org> Fri Sep 30 01:29:00 2005 +0000
tree 1a411f1d36e18d2fa0e33d9c7c6df9ff4481226c
parent 294f41d5fc713350f060656e562c34ddf1cbe1c6

Change this code ot pass register classes into the stack slot spiller/reloader
code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23536 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegMap.cpp

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index c958143..633cf2b 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -163,18 +163,20 @@
             unsigned PhysReg = VRM.getPhys(VirtReg);
             if (VRM.hasStackSlot(VirtReg)) {
               int StackSlot = VRM.getStackSlot(VirtReg);
+              const TargetRegisterClass* RC =
+                MF.getSSARegMap()->getRegClass(VirtReg);
 
               if (MO.isUse() &&
                   std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
                   == LoadedRegs.end()) {
-                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
                 LoadedRegs.push_back(VirtReg);
                 ++NumLoads;
                 DEBUG(std::cerr << '\t' << *prior(MII));
               }
 
               if (MO.isDef()) {
-                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
                 ++NumStores;
               }
             }
@@ -386,6 +388,8 @@
       
       // Otherwise, reload it and remember that we have it.
       PhysReg = VRM.getPhys(VirtReg);
+      const TargetRegisterClass* RC =
+        MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
 
     RecheckRegister:
       // Note that, if we reused a register for a previous operand, the
@@ -406,7 +410,7 @@
               // was used.  This isn't good because it means we have
               // to undo a previous reuse.
               MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
-                                        Op.StackSlot);
+                                        Op.StackSlot, RC);
               ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
                              PhysRegsAvailable);
 
@@ -431,7 +435,7 @@
           }
     ContinueReload:
       PhysRegsUsed[PhysReg] = true;
-      MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+      MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
       // This invalidates PhysReg.
       ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
 
@@ -553,6 +557,8 @@
         if (!TakenCareOf) {
           // The only vregs left are stack slot definitions.
           int StackSlot    = VRM.getStackSlot(VirtReg);
+          const TargetRegisterClass *RC =
+            MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
           unsigned PhysReg;
 
           // If this is a def&use operand, and we used a different physreg for
@@ -564,7 +570,7 @@
             PhysReg = MO.getReg();
 
           PhysRegsUsed[PhysReg] = true;
-          MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+          MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
           DEBUG(std::cerr << "Store:\t" << *next(MII));
           MI.SetMachineOperandReg(i, PhysReg);