diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 52026e2..1e9704e 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -200,7 +200,8 @@
   MachineBasicBlock::iterator I = MBB->begin();
   for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
     // Insert the spill to the stack frame.
-    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+    RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+                                 0 /*FIXME*/);
   }
 
   // Add code to restore the callee-save registers in each exiting block.
@@ -225,7 +226,8 @@
       // Restore all registers immediately before the return and any terminators
       // that preceed it.
       for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
-        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+        RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+                                      0 /*FIXME*/);
         assert(I != MBB->begin() &&
                "loadRegFromStackSlot didn't insert any code!");
         // Insert in reverse order.  loadRegFromStackSlot can insert multiple
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index cffc73c..7288f06 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -270,7 +270,7 @@
     const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
     int FrameIndex = getStackSpaceFor(VirtReg, RC);
     DEBUG(std::cerr << " to stack slot #" << FrameIndex);
-    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
+    RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
     ++NumStores;   // Update statistics
   }
 
@@ -476,7 +476,7 @@
                   << RegInfo->getName(PhysReg) << "\n");
 
   // Add move instruction(s)
-  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
+  RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
   ++NumLoads;    // Update statistics
 
   PhysRegsEverUsed[PhysReg] = true;
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index b27f1b7..57f3f5d 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -135,7 +135,7 @@
 
   // Add move instruction(s)
   ++NumLoads;
-  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
+  RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
   return PhysReg;
 }
 
@@ -147,7 +147,7 @@
 
   // Add move instruction(s)
   ++NumStores;
-  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
+  RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
 }
 
 
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index c958143..633cf2b 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -163,18 +163,20 @@
             unsigned PhysReg = VRM.getPhys(VirtReg);
             if (VRM.hasStackSlot(VirtReg)) {
               int StackSlot = VRM.getStackSlot(VirtReg);
+              const TargetRegisterClass* RC =
+                MF.getSSARegMap()->getRegClass(VirtReg);
 
               if (MO.isUse() &&
                   std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
                   == LoadedRegs.end()) {
-                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
                 LoadedRegs.push_back(VirtReg);
                 ++NumLoads;
                 DEBUG(std::cerr << '\t' << *prior(MII));
               }
 
               if (MO.isDef()) {
-                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
                 ++NumStores;
               }
             }
@@ -386,6 +388,8 @@
       
       // Otherwise, reload it and remember that we have it.
       PhysReg = VRM.getPhys(VirtReg);
+      const TargetRegisterClass* RC =
+        MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
 
     RecheckRegister:
       // Note that, if we reused a register for a previous operand, the
@@ -406,7 +410,7 @@
               // was used.  This isn't good because it means we have
               // to undo a previous reuse.
               MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
-                                        Op.StackSlot);
+                                        Op.StackSlot, RC);
               ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
                              PhysRegsAvailable);
 
@@ -431,7 +435,7 @@
           }
     ContinueReload:
       PhysRegsUsed[PhysReg] = true;
-      MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+      MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
       // This invalidates PhysReg.
       ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
 
@@ -553,6 +557,8 @@
         if (!TakenCareOf) {
           // The only vregs left are stack slot definitions.
           int StackSlot    = VRM.getStackSlot(VirtReg);
+          const TargetRegisterClass *RC =
+            MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
           unsigned PhysReg;
 
           // If this is a def&use operand, and we used a different physreg for
@@ -564,7 +570,7 @@
             PhysReg = MO.getReg();
 
           PhysRegsUsed[PhysReg] = true;
-          MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+          MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
           DEBUG(std::cerr << "Store:\t" << *next(MII));
           MI.SetMachineOperandReg(i, PhysReg);