ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 488c508..81a4a55 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -1172,3 +1172,9 @@
(VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
(VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
+
+// VMUL has a two-operand form (implied destination operand)
+def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm",
+ (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>;
+def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm",
+ (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>;
diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s
index 5c81c78..fc0c7c9 100644
--- a/test/MC/ARM/simple-fp-encoding.s
+++ b/test/MC/ARM/simple-fp-encoding.s
@@ -21,9 +21,15 @@
@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
vmul.f64 d16, d17, d16
+@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee]
+ vmul.f64 d20, d17
+
@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
vmul.f32 s0, s1, s0
+@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee]
+ vmul.f32 s11, s21
+
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
vnmul.f64 d16, d17, d16