* Rename X86::IMULr16 -> X86::IMULrr16
* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
extra copy into a register, reducing register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9278 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index aaebb5b..b2e656a 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -722,19 +722,24 @@
}
case X86II::MRMSrcReg: {
- // There is a two forms that are acceptable for MRMSrcReg instructions,
+ // There is are three forms that are acceptable for MRMSrcReg instructions,
// those with 3 and 2 operands:
//
// 3 Operands: in this form, the last register (the second input) is the
// ModR/M input. The first two operands should be the same, post register
// allocation. This is for things like: add r32, r/m32
//
+ // 3 Operands: in this form, we can have 'INST R, R, imm', which is used for
+ // instructions like the IMULri instructions.
+ //
// 2 Operands: this is for things like mov that do not read a second input
//
assert(MI->getOperand(0).isRegister() &&
MI->getOperand(1).isRegister() &&
(MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
+ (MI->getNumOperands() == 3 &&
+ (MI->getOperand(2).isRegister() ||
+ MI->getOperand(2).isImmediate())))
&& "Bad format for MRMSrcReg!");
if (MI->getNumOperands() == 3 &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
@@ -742,6 +747,13 @@
O << TII.getName(MI->getOpCode()) << " ";
printOp(MI->getOperand(0));
+
+ // If this is IMULri* instructions, print the non-two-address operand.
+ if (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()) {
+ O << ", ";
+ printOp(MI->getOperand(1));
+ }
+
O << ", ";
printOp(MI->getOperand(MI->getNumOperands()-1));
O << "\n";