Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 7d2ecec..f01196a 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -630,8 +630,8 @@
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
- if (! mii.isNop((*I)->getOpcode()) &&
- ! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isNop(I->getOpcode()) &&
+ ! mii.isDummyPhiInstr(I->getOpcode()))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
@@ -643,12 +643,12 @@
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
- if (! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isDummyPhiInstr(I->getOpcode()))
break;
- // Erase all except the dummy PHI instructions from MBB, and
+ // Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- MBB.erase(I, MBB.end());
+ while (I != MBB.end()) MBB.remove(I);
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
@@ -1175,25 +1175,25 @@
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
- assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
+ assert(&MBB[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(MBB[i]->getOpcode()))
+ if (! mii.isNop(MBB[i].getOpcode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(MBB[i]));
+ graph->getGraphNodeForInstr(&MBB[i]));
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(MBB[i]->getOpcode()))
+ if (mii.isNop(MBB[i].getOpcode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
else {
- nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
@@ -1202,7 +1202,7 @@
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if (*mciI==MBB[i])
+ if (*mciI == &MBB[i])
llvmMvec.erase(mciI);
}
}
@@ -1282,10 +1282,10 @@
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
- if (MBB[i] != brInstr &&
- mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
+ if (&MBB[i] != brInstr &&
+ mii.getNumDelaySlots(MBB[i].getOpcode()) > 0)
{
- SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* node = graph->getGraphNodeForInstr(&MBB[i]);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index fe150c2..01ca36f 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -53,7 +53,8 @@
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
+ MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
if (MI) {
MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode)
@@ -183,10 +184,10 @@
// all preceding instructions in the basic block. Use 0 latency again.
//
for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (MBB[i] == termMvec[first]) // reached the first branch
+ if (&MBB[i] == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
@@ -198,11 +199,11 @@
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
+ unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
@@ -554,9 +555,9 @@
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
+ if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(MBB[i], node);
+ noteGraphNodeForInstr(&MBB[i], node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -632,7 +633,7 @@
// Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+ addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index caa9e2e..9bee895 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -92,7 +92,7 @@
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) {
- inserted = mi2iMap_.insert(std::make_pair(*mi, miIndex)).second;
+ inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second;
assert(inserted && "multiple MachineInstr -> index mappings");
miIndex += 2;
}
@@ -109,12 +109,10 @@
const MachineBasicBlock* mbb = mbbi;
unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
- for (MachineBasicBlock::const_iterator mii = mbb->begin(),
- mie = mbb->end(); mii != mie; ++mii) {
- MachineInstr* mi = *mii;
-
+ for (MachineBasicBlock::const_iterator mi = mbb->begin(),
+ mie = mbb->end(); mi != mie; ++mi) {
for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = mi->getOperand(i);
+ const MachineOperand& mop = mi->getOperand(i);
if (mop.isRegister() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
unsigned reg = mop.getAllocatedRegNum();
@@ -169,8 +167,8 @@
if (vi.AliveBlocks[i]) {
MachineBasicBlock* mbb = lv_->getIndexMachineBasicBlock(i);
if (!mbb->empty()) {
- interval->addRange(getInstructionIndex(mbb->front()),
- getInstructionIndex(mbb->back()) + 1);
+ interval->addRange(getInstructionIndex(&mbb->front()),
+ getInstructionIndex(&mbb->back()) + 1);
}
}
}
@@ -181,7 +179,7 @@
// we consider defs to happen at the second time slot of the
// instruction
- unsigned instrIndex = getInstructionIndex(*mi) + 1;
+ unsigned instrIndex = getInstructionIndex(mi) + 1;
bool killedInDefiningBasicBlock = false;
for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
@@ -189,8 +187,8 @@
MachineInstr* killerInstr = vi.Kills[i].second;
unsigned start = (mbb == killerBlock ?
instrIndex :
- getInstructionIndex(killerBlock->front()));
- unsigned end = (killerInstr == *mi ?
+ getInstructionIndex(&killerBlock->front()));
+ unsigned end = (killerInstr == mi ?
instrIndex + 1 : // dead
getInstructionIndex(killerInstr) + 1); // killed
// we do not want to add invalid ranges. these can happen when
@@ -204,7 +202,7 @@
}
if (!killedInDefiningBasicBlock) {
- unsigned end = getInstructionIndex(mbb->back()) + 1;
+ unsigned end = getInstructionIndex(&mbb->back()) + 1;
interval->addRange(instrIndex, end);
}
}
@@ -221,10 +219,10 @@
// we consider defs to happen at the second time slot of the
// instruction
unsigned start, end;
- start = end = getInstructionIndex(*mi) + 1;
+ start = end = getInstructionIndex(mi) + 1;
// a variable can be dead by the instruction defining it
- for (KillIter ki = lv_->dead_begin(*mi), ke = lv_->dead_end(*mi);
+ for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi);
ki != ke; ++ki) {
if (reg == ki->second) {
DEBUG(std::cerr << " dead\n");
@@ -237,7 +235,7 @@
do {
++mi;
end += 2;
- for (KillIter ki = lv_->killed_begin(*mi), ke = lv_->killed_end(*mi);
+ for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi);
ki != ke; ++ki) {
if (reg == ki->second) {
DEBUG(std::cerr << " killed\n");
@@ -301,19 +299,18 @@
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) {
- MachineInstr* instr = *mi;
const TargetInstrDescriptor& tid =
- tm_->getInstrInfo().get(instr->getOpcode());
- DEBUG(std::cerr << "\t[" << getInstructionIndex(instr) << "] ";
- instr->print(std::cerr, *tm_););
+ tm_->getInstrInfo().get(mi->getOpcode());
+ DEBUG(std::cerr << "\t[" << getInstructionIndex(mi) << "] ";
+ mi->print(std::cerr, *tm_););
// handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
handleRegisterDef(mbb, mi, *id);
// handle explicit defs
- for (int i = instr->getNumOperands() - 1; i >= 0; --i) {
- MachineOperand& mop = instr->getOperand(i);
+ for (int i = mi->getNumOperands() - 1; i >= 0; --i) {
+ MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
if (mop.isRegister() && mop.isDef())
handleRegisterDef(mbb, mi, mop.getAllocatedRegNum());
@@ -336,15 +333,14 @@
const TargetInstrInfo& tii = tm_->getInstrInfo();
- for (MachineFunction::const_iterator mbbi = mf_->begin(),
- mbbe = mf_->end(); mbbi != mbbe; ++mbbi) {
- const MachineBasicBlock* mbb = mbbi;
+ for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
+ mbbi != mbbe; ++mbbi) {
+ MachineBasicBlock* mbb = mbbi;
DEBUG(std::cerr << "machine basic block: "
<< mbb->getBasicBlock()->getName() << "\n");
- for (MachineBasicBlock::const_iterator mii = mbb->begin(),
- mie = mbb->end(); mii != mie; ++mii) {
- MachineInstr* mi = *mii;
+ for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
+ mi != mie; ++mi) {
const TargetInstrDescriptor& tid =
tm_->getInstrInfo().get(mi->getOpcode());
DEBUG(std::cerr << "\t\tinstruction["
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index fcc78c0..420cb44 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -213,7 +213,7 @@
// Loop over all of the instructions, processing them.
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Process all of the operands of the instruction...
@@ -275,9 +275,8 @@
MachineBasicBlock *Succ = BBMap.find(*SI)->second.first;
// PHI nodes are guaranteed to be at the top of the block...
- for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end();
- I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) {
- MachineInstr *MI = *I;
+ for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
+ MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
for (unsigned i = 1; ; i += 2)
if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) {
MachineOperand &MO = MI->getOperand(i);
diff --git a/lib/CodeGen/MachineCodeForInstruction.cpp b/lib/CodeGen/MachineCodeForInstruction.cpp
index 50a5409..9d63df5 100644
--- a/lib/CodeGen/MachineCodeForInstruction.cpp
+++ b/lib/CodeGen/MachineCodeForInstruction.cpp
@@ -60,9 +60,8 @@
for (unsigned i=0, N=tempVec.size(); i < N; i++)
delete tempVec[i];
- // Free the MachineInstr objects allocated, if any.
- for (unsigned i=0, N = size(); i < N; i++)
- delete (*this)[i];
+ // do not free the MachineInstr objects allocated. they are managed
+ // by the ilist in MachineBasicBlock
// Free the CallArgsDescriptor if it exists.
delete callArgsDesc;
diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp
index 6c15ad5..4de55f4 100644
--- a/lib/CodeGen/MachineFunction.cpp
+++ b/lib/CodeGen/MachineFunction.cpp
@@ -62,34 +62,6 @@
return new Printer(OS, Banner);
}
-namespace {
- struct Deleter : public MachineFunctionPass {
- const char *getPassName() const { return "Machine Code Deleter"; }
-
- bool runOnMachineFunction(MachineFunction &MF) {
- // Delete all of the MachineInstrs out of the function. When the sparc
- // backend gets fixed, this can be dramatically simpler, but actually
- // putting this stuff into the MachineBasicBlock destructor!
- for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E;
- ++BB)
- while (!BB->empty())
- delete BB->pop_back();
-
- // Delete the annotation from the function now.
- MachineFunction::destruct(MF.getFunction());
- return true;
- }
- };
-}
-
-/// MachineCodeDeletion Pass - This pass deletes all of the machine code for
-/// the current function, which should happen after the function has been
-/// emitted to a .s file or to memory.
-FunctionPass *llvm::createMachineCodeDeleter() {
- return new Deleter();
-}
-
-
//===---------------------------------------------------------------------===//
// MachineFunction implementation
//===---------------------------------------------------------------------===//
@@ -127,7 +99,7 @@
OS << "\n" << LBB->getName() << " (" << (const void*)LBB << "):\n";
for (MachineBasicBlock::const_iterator I = BB->begin(); I != BB->end();++I){
OS << "\t";
- (*I)->print(OS, Target);
+ I->print(OS, Target);
}
}
OS << "\nEnd function \"" << Fn->getName() << "\"\n\n";
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index afb87e5..03a1da9 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -61,18 +61,18 @@
/// predecessor basic blocks.
///
bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
- if (MBB.empty() || MBB.front()->getOpcode() != TargetInstrInfo::PHI)
+ if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI)
return false; // Quick exit for normal case...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
const TargetInstrInfo &MII = MF.getTarget().getInstrInfo();
const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- while (MBB.front()->getOpcode() == TargetInstrInfo::PHI) {
- MachineInstr *MI = MBB.front();
+ while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
// Unlink the PHI node from the basic block... but don't delete the PHI yet
- MBB.erase(MBB.begin());
-
+ MachineBasicBlock::iterator begin = MBB.begin();
+ MachineInstr *MI = MBB.remove(begin);
+
assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
@@ -88,13 +88,13 @@
//
MachineBasicBlock::iterator AfterPHIsIt = MBB.begin();
while (AfterPHIsIt != MBB.end() &&
- (*AfterPHIsIt)->getOpcode() == TargetInstrInfo::PHI)
+ AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI)
++AfterPHIsIt; // Skip over all of the PHI nodes...
RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
// Update live variable information if there is any...
if (LV) {
- MachineInstr *PHICopy = *(AfterPHIsIt-1);
+ MachineInstr *PHICopy = --AfterPHIsIt;
// Add information to LiveVariables to know that the incoming value is
// killed. Note that because the value is defined in several places (once
@@ -149,13 +149,13 @@
if (I != opBlock.begin()) { // Handle empty blocks
--I;
// must backtrack over ALL the branches in the previous block
- while (MII.isTerminatorInstr((*I)->getOpcode()) &&
+ while (MII.isTerminatorInstr(I->getOpcode()) &&
I != opBlock.begin())
--I;
// move back to the first branch instruction so new instructions
// are inserted right in front of it and not in front of a non-branch
- if (!MII.isTerminatorInstr((*I)->getOpcode()))
+ if (!MII.isTerminatorInstr(I->getOpcode()))
++I;
}
@@ -171,7 +171,8 @@
bool HaveNotEmitted = true;
if (I != opBlock.begin()) {
- MachineInstr *PrevInst = *(I-1);
+ MachineBasicBlock::iterator PrevInst = I;
+ --PrevInst;
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
if (MO.isRegister() && MO.getReg() == IncomingReg)
@@ -238,10 +239,10 @@
// Loop over all of the PHIs in this successor, checking to see if
// the register is being used...
for (MachineBasicBlock::iterator BBI = MBB->begin(), E=MBB->end();
- BBI != E && (*BBI)->getOpcode() == TargetInstrInfo::PHI;
+ BBI != E && BBI->getOpcode() == TargetInstrInfo::PHI;
++BBI)
- for (unsigned i = 1, e = (*BBI)->getNumOperands(); i < e; i += 2)
- if ((*BBI)->getOperand(i).getReg() == SrcReg) {
+ for (unsigned i = 1, e = BBI->getNumOperands(); i < e; i += 2)
+ if (BBI->getOperand(i).getReg() == SrcReg) {
ValueIsLive = true;
break;
}
@@ -251,8 +252,11 @@
// we can add a kill marker to the copy we inserted saying that it
// kills the incoming value!
//
- if (!ValueIsLive)
- LV->addVirtualRegisterKilled(SrcReg, &opBlock, *(I-1));
+ if (!ValueIsLive) {
+ MachineBasicBlock::iterator Prev = I;
+ --Prev;
+ LV->addVirtualRegisterKilled(SrcReg, &opBlock, Prev);
+ }
}
}
}
@@ -260,7 +264,6 @@
// really delete the PHI instruction now!
delete MI;
}
-
return true;
}
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 79406f9..8f34cf4 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -105,17 +105,17 @@
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); )
- if ((*I)->getOpcode() == FrameSetupOpcode ||
- (*I)->getOpcode() == FrameDestroyOpcode) {
- assert((*I)->getNumOperands() == 1 && "Call Frame Setup/Destroy Pseudo"
+ if (I->getOpcode() == FrameSetupOpcode ||
+ I->getOpcode() == FrameDestroyOpcode) {
+ assert(I->getNumOperands() == 1 && "Call Frame Setup/Destroy Pseudo"
" instructions should have a single immediate argument!");
- unsigned Size = (*I)->getOperand(0).getImmedValue();
+ unsigned Size = I->getOperand(0).getImmedValue();
if (Size > MaxCallFrameSize) MaxCallFrameSize = Size;
HasCalls = true;
- RegInfo->eliminateCallFramePseudoInstr(Fn, *BB, I);
+ RegInfo->eliminateCallFramePseudoInstr(Fn, *BB, I++);
} else {
- for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = (*I)->getOperand(i);
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef()) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Register allocation must be performed!");
@@ -174,8 +174,9 @@
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
- if (!FI->empty() && TII.isReturn(FI->back()->getOpcode())) {
- MBB = FI; I = MBB->end()-1;
+ if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
+ MBB = FI;
+ I = MBB->end(); --I;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
const TargetRegisterClass *RC = RegInfo->getRegClass(RegsToSave[i]);
@@ -235,7 +236,7 @@
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && TII.isReturn(I->back()->getOpcode()))
+ if (!I->empty() && TII.isReturn(I->back().getOpcode()))
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
@@ -253,8 +254,8 @@
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB)
for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I)
- for (unsigned i = 0, e = (*I)->getNumOperands(); i != e; ++i)
- if ((*I)->getOperand(i).isFrameIndex()) {
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
+ if (I->getOperand(i).isFrameIndex()) {
// If this instruction has a FrameIndex operand, we need to use that
// target machine register info object to eliminate it.
MRI.eliminateFrameIndex(Fn, I);
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 9df824a..b9d6f08 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -396,15 +396,15 @@
for (currentInstr_ = currentMbb_->begin();
currentInstr_ != currentMbb_->end(); ) {
DEBUG(std::cerr << "\tinstruction: ";
- (*currentInstr_)->print(std::cerr, *tm_););
+ currentInstr_->print(std::cerr, *tm_););
// use our current mapping and actually replace and
// virtual register with its allocated physical registers
DEBUG(std::cerr << "\t\treplacing virtual registers with mapped "
"physical registers:\n");
- for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
+ for (unsigned i = 0, e = currentInstr_->getNumOperands();
i != e; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getReg();
@@ -412,20 +412,19 @@
if (it != v2pMap_.end()) {
DEBUG(std::cerr << "\t\t\t%reg" << it->first
<< " -> " << mri_->getName(it->second) << '\n');
- (*currentInstr_)->SetMachineOperandReg(i, it->second);
+ currentInstr_->SetMachineOperandReg(i, it->second);
}
}
}
unsigned srcReg, dstReg;
- if (tii.isMoveInstr(**currentInstr_, srcReg, dstReg) &&
+ if (tii.isMoveInstr(*currentInstr_, srcReg, dstReg) &&
((MRegisterInfo::isPhysicalRegister(srcReg) &&
MRegisterInfo::isPhysicalRegister(dstReg) &&
srcReg == dstReg) ||
(MRegisterInfo::isVirtualRegister(srcReg) &&
MRegisterInfo::isVirtualRegister(dstReg) &&
v2ssMap_[srcReg] == v2ssMap_[dstReg]))) {
- delete *currentInstr_;
currentInstr_ = currentMbb_->erase(currentInstr_);
++numPeep;
DEBUG(std::cerr << "\t\tdeleting instruction\n");
@@ -436,12 +435,12 @@
Regs toClear;
Regs toSpill;
- const unsigned numOperands = (*currentInstr_)->getNumOperands();
+ const unsigned numOperands = currentInstr_->getNumOperands();
DEBUG(std::cerr << "\t\tloading temporarily used operands to "
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getAllocatedRegNum();
@@ -460,7 +459,7 @@
else
toClear.push_back(it);
}
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
+ currentInstr_->SetMachineOperandReg(i, physReg);
}
}
@@ -472,7 +471,7 @@
DEBUG(std::cerr << "\t\tassigning temporarily defined operands to "
"registers:\n");
for (unsigned i = 0; i != numOperands; ++i) {
- MachineOperand& op = (*currentInstr_)->getOperand(i);
+ MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
assert(!op.isUse() && "we should not have uses here!");
@@ -489,7 +488,7 @@
// this instruction
toSpill.push_back(it);
}
- (*currentInstr_)->SetMachineOperandReg(i, physReg);
+ currentInstr_->SetMachineOperandReg(i, physReg);
}
}
++currentInstr_; // spills will go after this instruction
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 3f53106..152aec4 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -496,9 +496,8 @@
void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- MachineBasicBlock::iterator I = MBB.begin();
- for (; I != MBB.end(); ++I) {
- MachineInstr *MI = *I;
+ MachineBasicBlock::iterator MI = MBB.begin();
+ for (; MI != MBB.end(); ++MI) {
const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: ";
@@ -525,7 +524,7 @@
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
- unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
+ unsigned PhysSrcReg = reloadVirtReg(MBB, MI, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
}
@@ -559,7 +558,7 @@
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
- spillPhysReg(MBB, I, Reg, true); // Spill any existing value in the reg
+ spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
@@ -573,7 +572,7 @@
for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
*ImplicitDefs; ++ImplicitDefs) {
unsigned Reg = *ImplicitDefs;
- spillPhysReg(MBB, I, Reg);
+ spillPhysReg(MBB, MI, Reg);
PhysRegsUseOrder.push_back(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
@@ -596,7 +595,7 @@
// If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getOrInsertVirt2PhysRegMapSlot(DestVirtReg)))
- DestPhysReg = getReg(MBB, I, DestVirtReg);
+ DestPhysReg = getReg(MBB, MI, DestVirtReg);
markVirtRegModified(DestVirtReg);
MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
}
@@ -628,15 +627,15 @@
// Rewind the iterator to point to the first flow control instruction...
const TargetInstrInfo &TII = TM->getInstrInfo();
- I = MBB.end();
- while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
- --I;
+ MI = MBB.end();
+ while (MI != MBB.begin() && TII.isTerminatorInstr((--MI)->getOpcode()));
+ ++MI;
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
if (PhysRegsUsed[i] != -1)
if (unsigned VirtReg = PhysRegsUsed[i])
- spillVirtReg(MBB, I, VirtReg, i);
+ spillVirtReg(MBB, MI, VirtReg, i);
else
removePhysReg(i);
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index ac76220..a40ec64 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -150,12 +150,10 @@
void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
+ for (MachineBasicBlock::iterator MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- MachineInstr *MI = *I;
-
RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
// a preliminary pass that will invalidate any registers that
@@ -197,11 +195,11 @@
} else {
physReg = getFreeReg(virtualReg);
}
- ++I;
- spillVirtReg(MBB, I, virtualReg, physReg);
- --I;
+ ++MI;
+ spillVirtReg(MBB, MI, virtualReg, physReg);
+ --MI;
} else {
- physReg = reloadVirtReg(MBB, I, virtualReg);
+ physReg = reloadVirtReg(MBB, MI, virtualReg);
Virt2PhysRegMap[virtualReg] = physReg;
}
}
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 497cf63..3f99f2a 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -84,9 +84,8 @@
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
- for (MachineBasicBlock::iterator mii = mbbi->begin();
- mii != mbbi->end(); ++mii) {
- MachineInstr* mi = *mii;
+ for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
+ mi != me; ++mi) {
unsigned opcode = mi->getOpcode();
// ignore if it is not a two-address instruction
@@ -132,10 +131,11 @@
const TargetRegisterClass* rc =
MF.getSSARegMap()->getRegClass(regA);
- unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
+ unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
numInstrsAdded += Added;
- MachineInstr* prevMi = *(mii - 1);
+ MachineBasicBlock::iterator prevMi = mi;
+ --prevMi;
DEBUG(std::cerr << "\t\tadded instruction: ";
prevMi->print(std::cerr, TM));