temporarily revert the patch due to some conflicts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175107 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 58c7798..986dfb7 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -342,11 +342,6 @@
unsigned Reg = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
assert(!MO.getSubReg() && "Subregs should be eliminated!");
- if(ARM::GPRPairRegClass.contains(Reg)) {
- const MachineFunction &MF = *MI->getParent()->getParent();
- const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
- Reg = TRI->getSubReg(Reg, ARM::gsub_0);
- }
O << ARMInstPrinter::getRegisterName(Reg);
break;
}
@@ -535,12 +530,14 @@
const MachineOperand &MO = MI->getOperand(OpNum);
if (!MO.isReg())
return true;
+ const TargetRegisterClass &RC = ARM::GPRRegClass;
const MachineFunction &MF = *MI->getParent()->getParent();
const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
- unsigned Reg = MO.getReg();
- if(!ARM::GPRPairRegClass.contains(Reg))
- return false;
- Reg = TRI->getSubReg(Reg, ARM::gsub_1);
+
+ unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
+ RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
+
+ unsigned Reg = RC.getRegister(RegIdx);
O << ARMInstPrinter::getRegisterName(Reg);
return false;
}