commit c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9
author Cameron Zwarich <zwarich@apple.com> Wed Mar 30 23:01:21 2011 +0000
committer Cameron Zwarich <zwarich@apple.com> Wed Mar 30 23:01:21 2011 +0000
tree ec953e12dc862895c78118ce64ecc6240cb92a11
parent f5b23368d27ef7dd44b2c45b5c08812ac99c7661

Add a ARM-specific SD node for VBSL so that forms with a constant first operand
can be recognized. This fixes <rdar://problem/9183078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.h

diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index e09c1da..e37855d 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -179,6 +179,9 @@
       // Vector AND with NOT of immediate
       VBICIMM,
 
+      // Vector bitwise select
+      VBSL,
+
       // Vector load N-element structure to all lanes:
       VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
       VLD3DUP,