Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 5330306..e72cdc6 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -395,7 +395,7 @@
#endif
// Create the new machine instruction.
- MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
+ MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
@@ -518,7 +518,7 @@
// Create the inline asm machine instruction.
MachineInstr *MI =
- new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+ new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index c18b5bc..0257e1b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -294,8 +294,9 @@
}
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
+ const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
for (unsigned i = 0; i != NumElements; ++i)
- BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
+ BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
}
}
}