commit c1b46f91f52ea838be6d67708a43ff661810fe6a
author Evan Cheng <evan.cheng@apple.com> Fri Jul 17 00:32:06 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Fri Jul 17 00:32:06 2009 +0000
tree e774c5c0dc10c9feff4ff5c2c92dfe2fb11bf3e6
parent 28ebfcf7de02fdd8154b15b5f0d1f9b43dfc4a6f

Fix my brain cramp by inverting the assertion condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76131 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegRewriter.cpp

diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 2213c65..abaa8bd 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -491,13 +491,11 @@
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
   MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
-#if 0
 #ifndef NDEBUG
   const TargetInstrDesc &TID = ReMatDefMI->getDesc();
-  assert(TID.getNumDefs() != 1 &&
+  assert(TID.getNumDefs() == 1 &&
          "Don't know how to remat instructions that define > 1 values!");
 #endif
-#endif
   TII->reMaterialize(MBB, MII, DestReg,
                      ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
   MachineInstr *NewMI = prior(MII);