Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183565 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 5ec54a6..b93f5e4 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -39,11 +39,10 @@
/// layout, etc.
///
TargetMachine &TM;
- const TargetInstrInfo *TII;
static char ID;
Filler(TargetMachine &tm)
- : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
+ : MachineFunctionPass(ID), TM(tm) { }
virtual const char *getPassName() const {
return "SPARC Delay Slot Filler";
@@ -127,6 +126,7 @@
++FilledSlots;
Changed = true;
+ const TargetInstrInfo *TII = TM.getInstrInfo();
if (D == MBB.end())
BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
else
@@ -166,7 +166,7 @@
if (J->getOpcode() == SP::RESTORErr
|| J->getOpcode() == SP::RESTOREri) {
// change retl to ret.
- slot->setDesc(TII->get(SP::RET));
+ slot->setDesc(TM.getInstrInfo()->get(SP::RET));
return J;
}
}
@@ -476,6 +476,8 @@
if (isDelayFiller(MBB, PrevInst))
return false;
+ const TargetInstrInfo *TII = TM.getInstrInfo();
+
switch (PrevInst->getOpcode()) {
default: break;
case SP::ADDrr: