llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index f160bd0..c726ccc 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -55,7 +55,7 @@
else if (Subtarget->isTargetELF())
O << ".Lllvm$" << getFunctionNumber() << ".$piclabel";
else
- LLVM_UNREACHABLE("Don't know how to print PIC label!");
+ llvm_unreachable("Don't know how to print PIC label!");
}
/// PrintUnmangledNameSafely - Print out the printable characters in the name.
@@ -155,7 +155,7 @@
}
break;
default:
- LLVM_UNREACHABLE("Unsupported DecorationStyle");
+ llvm_unreachable("Unsupported DecorationStyle");
}
}
@@ -167,7 +167,7 @@
SwitchToSection(TAI->SectionForGlobal(F));
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unknown linkage type!");
+ default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
EmitAlignment(FnAlign, F);
@@ -292,7 +292,7 @@
/// which print to a label with various suffixes for relocation types etc.
void X86ATTAsmPrinter::printSymbolOperand(const MachineOperand &MO) {
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("unknown symbol type!");
+ default: llvm_unreachable("unknown symbol type!");
case MachineOperand::MO_JumpTableIndex:
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << '_'
<< MO.getIndex();
@@ -366,7 +366,7 @@
switch (MO.getTargetFlags()) {
default:
- LLVM_UNREACHABLE("Unknown target flag on GV operand");
+ llvm_unreachable("Unknown target flag on GV operand");
case X86II::MO_NO_FLAG: // No flag.
break;
case X86II::MO_DARWIN_NONLAZY:
@@ -404,7 +404,7 @@
void X86ATTAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ default: llvm_unreachable("Unknown pcrel immediate operand");
case MachineOperand::MO_Immediate:
O << MO.getImm();
return;
@@ -426,7 +426,7 @@
const char *Modifier) {
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("unknown operand type!");
+ default: llvm_unreachable("unknown operand type!");
case MachineOperand::MO_Register: {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
@@ -735,7 +735,7 @@
} else if (MO.isMBB()) {
MCOp.MakeMBBLabel(getFunctionNumber(), MO.getMBB()->getNumber());
} else {
- LLVM_UNREACHABLE("Unimp");
+ llvm_unreachable("Unimp");
}
TmpInst.addOperand(MCOp);
@@ -887,7 +887,7 @@
case GlobalValue::InternalLinkage:
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
EmitAlignment(Align, GVar);
diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
index c3780d9..e0fa83a 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp
@@ -28,7 +28,7 @@
void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) {
switch (MI->getOperand(Op).getImm()) {
- default: LLVM_UNREACHABLE("Invalid ssecc argument!");
+ default: llvm_unreachable("Invalid ssecc argument!");
case 0: O << "eq"; break;
case 1: O << "lt"; break;
case 2: O << "le"; break;
@@ -42,7 +42,7 @@
void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) {
- LLVM_UNREACHABLE("This is only used for MOVPC32r,"
+ llvm_unreachable("This is only used for MOVPC32r,"
"should lower before asm printing!");
}
@@ -61,7 +61,7 @@
O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction()
<< '_' << Op.getMBBLabelBlock();
else
- LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ llvm_unreachable("Unknown pcrel immediate operand");
}
@@ -104,7 +104,7 @@
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
O << DispVal;
} else {
- LLVM_UNREACHABLE("non-immediate displacement for LEA?");
+ llvm_unreachable("non-immediate displacement for LEA?");
//assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
// DispSpec.isJTI() || DispSpec.isSymbol());
//printOperand(MI, Op+3, "mem");
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
index 793616e..9890fdd 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
@@ -115,7 +115,7 @@
break;
default:
- LLVM_UNREACHABLE("Unsupported DecorationStyle");
+ llvm_unreachable("Unsupported DecorationStyle");
}
}
@@ -144,7 +144,7 @@
SwitchToTextSection("_text", F);
switch (F->getLinkage()) {
- default: LLVM_UNREACHABLE("Unsupported linkage type!");
+ default: llvm_unreachable("Unsupported linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
EmitAlignment(FnAlign);
@@ -268,7 +268,7 @@
void X86IntelAsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
switch (MO.getType()) {
- default: LLVM_UNREACHABLE("Unknown pcrel immediate operand");
+ default: llvm_unreachable("Unknown pcrel immediate operand");
case MachineOperand::MO_Immediate:
O << MO.getImm();
return;
@@ -520,7 +520,7 @@
SwitchToSection(TAI->getDataSection());
break;
default:
- LLVM_UNREACHABLE("Unknown linkage type!");
+ llvm_unreachable("Unknown linkage type!");
}
if (!bCustomSegment)
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index acaeea3..30bbc5c 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -335,7 +335,7 @@
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
} else {
- LLVM_UNREACHABLE("Unknown value to relocate!");
+ llvm_unreachable("Unknown value to relocate!");
}
}
@@ -478,7 +478,7 @@
case X86II::GS:
MCE.emitByte(0x65);
break;
- default: LLVM_UNREACHABLE("Invalid segment!");
+ default: llvm_unreachable("Invalid segment!");
case 0: break; // No segment override!
}
@@ -513,7 +513,7 @@
(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
>> X86II::Op0Shift));
break; // Two-byte opcode prefix
- default: LLVM_UNREACHABLE("Invalid prefix!");
+ default: llvm_unreachable("Invalid prefix!");
case 0: break; // No prefix!
}
@@ -548,13 +548,13 @@
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
switch (Desc->TSFlags & X86II::FormMask) {
- default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!");
+ default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
// Remember the current PC offset, this is the PIC relocation
// base address.
switch (Opcode) {
default:
- LLVM_UNREACHABLE("psuedo instructions should be removed before code emission");
+ llvm_unreachable("psuedo instructions should be removed before code emission");
break;
case TargetInstrInfo::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
@@ -620,7 +620,7 @@
} else
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
} else {
- LLVM_UNREACHABLE("Unknown RawFrm operand!");
+ llvm_unreachable("Unknown RawFrm operand!");
}
}
break;
@@ -811,7 +811,7 @@
#ifndef NDEBUG
cerr << "Cannot encode: " << MI << "\n";
#endif
- llvm_unreachable();
+ llvm_unreachable(0);
}
}
diff --git a/lib/Target/X86/X86ELFWriterInfo.cpp b/lib/Target/X86/X86ELFWriterInfo.cpp
index 9be7021..a26fe8c 100644
--- a/lib/Target/X86/X86ELFWriterInfo.cpp
+++ b/lib/Target/X86/X86ELFWriterInfo.cpp
@@ -43,7 +43,7 @@
return R_X86_64_64;
case X86::reloc_picrel_word:
default:
- LLVM_UNREACHABLE("unknown relocation type");
+ llvm_unreachable("unknown relocation type");
}
} else {
switch(MachineRelTy) {
@@ -54,7 +54,7 @@
case X86::reloc_absolute_dword:
case X86::reloc_picrel_word:
default:
- LLVM_UNREACHABLE("unknown relocation type");
+ llvm_unreachable("unknown relocation type");
}
}
return 0;
@@ -66,7 +66,7 @@
case R_X86_64_PC32: return -4;
break;
default:
- LLVM_UNREACHABLE("unknown x86 relocation type");
+ llvm_unreachable("unknown x86 relocation type");
}
}
return 0;
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 2b3304d..11919d9 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -1319,7 +1319,7 @@
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt: {
bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index c15e348..14bffdc 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -256,7 +256,7 @@
case X86II::CompareFP: handleCompareFP(I); break;
case X86II::CondMovFP: handleCondMovFP(I); break;
case X86II::SpecialFP: handleSpecialFP(I); break;
- default: LLVM_UNREACHABLE("Unknown FP Type!");
+ default: llvm_unreachable("Unknown FP Type!");
}
// Check to see if any of the values defined by this instruction are dead
@@ -946,7 +946,7 @@
MachineInstr *MI = I;
DebugLoc dl = MI->getDebugLoc();
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown SpecialFP instruction!");
+ default: llvm_unreachable("Unknown SpecialFP instruction!");
case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 8aa627f..296a4d3 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1462,7 +1462,7 @@
bool isSigned = Opcode == ISD::SMUL_LOHI;
if (!isSigned)
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
@@ -1470,7 +1470,7 @@
}
else
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
@@ -1479,7 +1479,7 @@
unsigned LoReg, HiReg;
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
@@ -1568,7 +1568,7 @@
bool isSigned = Opcode == ISD::SDIVREM;
if (!isSigned)
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
@@ -1576,7 +1576,7 @@
}
else
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
@@ -1586,7 +1586,7 @@
unsigned LoReg, HiReg;
unsigned ClrOpcode, SExtOpcode;
switch (NVT.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Unsupported VT!");
+ default: llvm_unreachable("Unsupported VT!");
case MVT::i8:
LoReg = X86::AL; HiReg = X86::AH;
ClrOpcode = 0;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1e79c4d..a2fedaf 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1426,7 +1426,7 @@
}
}
} else {
- LLVM_UNREACHABLE("Unknown argument type!");
+ llvm_unreachable("Unknown argument type!");
}
unsigned Reg = DAG.getMachineFunction().addLiveIn(VA.getLocReg(), RC);
@@ -1721,7 +1721,7 @@
// Promote the value if needed.
switch (VA.getLocInfo()) {
- default: LLVM_UNREACHABLE("Unknown loc info!");
+ default: llvm_unreachable("Unknown loc info!");
case CCValAssign::Full: break;
case CCValAssign::SExt:
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
@@ -2167,7 +2167,7 @@
}
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Invalid integer condition!");
+ default: llvm_unreachable("Invalid integer condition!");
case ISD::SETEQ: return X86::COND_E;
case ISD::SETGT: return X86::COND_G;
case ISD::SETGE: return X86::COND_GE;
@@ -2207,7 +2207,7 @@
// 1 | 0 | 0 | X == Y
// 1 | 1 | 1 | unordered
switch (SetCCOpcode) {
- default: LLVM_UNREACHABLE("Condcode should be pre-legalized away");
+ default: llvm_unreachable("Condcode should be pre-legalized away");
case ISD::SETUEQ:
case ISD::SETEQ: return X86::COND_E;
case ISD::SETOLT: // flipped
@@ -4715,7 +4715,7 @@
Subtarget->is64Bit());
}
- LLVM_UNREACHABLE("Unreachable");
+ llvm_unreachable("Unreachable");
return SDValue();
}
@@ -5038,7 +5038,7 @@
unsigned Opc;
switch (DstTy.getSimpleVT()) {
- default: LLVM_UNREACHABLE("Invalid FP_TO_SINT to lower!");
+ default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
@@ -5461,7 +5461,7 @@
NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
}
- LLVM_UNREACHABLE("Illegal FP comparison");
+ llvm_unreachable("Illegal FP comparison");
}
// Handle all other FP comparisons here.
return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
@@ -6247,7 +6247,7 @@
case Intrinsic::x86_mmx_psrai_d:
NewIntNo = Intrinsic::x86_mmx_psra_d;
break;
- default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here.
+ default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
}
break;
}
@@ -6397,7 +6397,7 @@
switch (CC) {
default:
- LLVM_UNREACHABLE("Unsupported calling convention");
+ llvm_unreachable("Unsupported calling convention");
case CallingConv::C:
case CallingConv::X86_StdCall: {
// Pass 'nest' parameter in ECX.
@@ -6646,7 +6646,7 @@
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Unknown ovf instruction!");
+ default: llvm_unreachable("Unknown ovf instruction!");
case ISD::SADDO:
// A subtract of one will be selected as a INC. Note that INC doesn't
// set CF, so we can't do this for UADDO.
@@ -6768,7 +6768,7 @@
///
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
- default: LLVM_UNREACHABLE("Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
@@ -7616,7 +7616,7 @@
// Get the X86 opcode to use.
unsigned Opc;
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("illegal opcode!");
+ default: llvm_unreachable("illegal opcode!");
case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
@@ -8355,7 +8355,7 @@
SDValue ValOp = N->getOperand(0);
switch (N->getOpcode()) {
default:
- LLVM_UNREACHABLE("Unknown shift opcode!");
+ llvm_unreachable("Unknown shift opcode!");
break;
case ISD::SHL:
if (VT == MVT::v2i64)
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 06e2b8d..6c06e58 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1300,7 +1300,7 @@
unsigned Opc;
unsigned Size;
switch (MI->getOpcode()) {
- default: LLVM_UNREACHABLE("Unreachable!");
+ default: llvm_unreachable("Unreachable!");
case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
@@ -1455,7 +1455,7 @@
unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case X86::COND_E: return X86::JE;
case X86::COND_NE: return X86::JNE;
case X86::COND_L: return X86::JL;
@@ -1479,7 +1479,7 @@
/// e.g. turning COND_E to COND_NE.
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case X86::COND_E: return X86::COND_NE;
case X86::COND_NE: return X86::COND_E;
case X86::COND_L: return X86::COND_GE;
@@ -1885,7 +1885,7 @@
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64mr;
} else {
- LLVM_UNREACHABLE("Unknown regclass");
+ llvm_unreachable("Unknown regclass");
}
return Opc;
@@ -1977,7 +1977,7 @@
} else if (RC == &X86::VR64RegClass) {
Opc = X86::MMX_MOVQ64rm;
} else {
- LLVM_UNREACHABLE("Unknown regclass");
+ llvm_unreachable("Unknown regclass");
}
return Opc;
@@ -2645,7 +2645,7 @@
case X86II::Imm16: return 2;
case X86II::Imm32: return 4;
case X86II::Imm64: return 8;
- default: LLVM_UNREACHABLE("Immediate size not set!");
+ default: llvm_unreachable("Immediate size not set!");
return 0;
}
}
@@ -2830,7 +2830,7 @@
} else if (RelocOp->isJTI()) {
FinalSize += sizeJumpTableAddress(false);
} else {
- LLVM_UNREACHABLE("Unknown value to relocate!");
+ llvm_unreachable("Unknown value to relocate!");
}
return FinalSize;
}
@@ -2927,7 +2927,7 @@
case X86II::GS:
++FinalSize;
break;
- default: LLVM_UNREACHABLE("Invalid segment!");
+ default: llvm_unreachable("Invalid segment!");
case 0: break; // No segment override!
}
@@ -2960,7 +2960,7 @@
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
++FinalSize;
break; // Two-byte opcode prefix
- default: LLVM_UNREACHABLE("Invalid prefix!");
+ default: llvm_unreachable("Invalid prefix!");
case 0: break; // No prefix!
}
@@ -2994,7 +2994,7 @@
--NumOps;
switch (Desc->TSFlags & X86II::FormMask) {
- default: LLVM_UNREACHABLE("Unknown FormMask value in X86 MachineCodeEmitter!");
+ default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
// Remember the current PC offset, this is the PIC relocation
// base address.
@@ -3039,7 +3039,7 @@
} else if (MO.isImm()) {
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
} else {
- LLVM_UNREACHABLE("Unknown RawFrm operand!");
+ llvm_unreachable("Unknown RawFrm operand!");
}
}
break;
diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp
index 4cc27ef..24e391e 100644
--- a/lib/Target/X86/X86JITInfo.cpp
+++ b/lib/Target/X86/X86JITInfo.cpp
@@ -322,7 +322,7 @@
#else // Not an i386 host
void X86CompilationCallback() {
- LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!");
+ llvm_unreachable("Cannot call X86CompilationCallback() on a non-x86 arch!");
}
#endif
}
@@ -554,7 +554,7 @@
TLSOffset -= size;
return TLSOffset;
#else
- LLVM_UNREACHABLE("Cannot allocate thread local storage on this arch!");
+ llvm_unreachable("Cannot allocate thread local storage on this arch!");
return 0;
#endif
}
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 3ae758b..437986f 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -147,7 +147,7 @@
default:
assert(isVirtualRegister(RegNo) && "Unknown physical register!");
- LLVM_UNREACHABLE("Register allocator hasn't allocated reg correctly yet!");
+ llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
return 0;
}
}
@@ -951,7 +951,7 @@
case X86::TAILJMPr:
case X86::TAILJMPm: break; // These are ok
default:
- LLVM_UNREACHABLE("Can only insert epilog into returning blocks");
+ llvm_unreachable("Can only insert epilog into returning blocks");
}
// Get the number of bytes to allocate from the FrameInfo
@@ -1104,12 +1104,12 @@
}
unsigned X86RegisterInfo::getEHExceptionRegister() const {
- LLVM_UNREACHABLE("What is the exception register");
+ llvm_unreachable("What is the exception register");
return 0;
}
unsigned X86RegisterInfo::getEHHandlerRegister() const {
- LLVM_UNREACHABLE("What is the exception handler register");
+ llvm_unreachable("What is the exception handler register");
return 0;
}
diff --git a/lib/Target/X86/X86TargetAsmInfo.cpp b/lib/Target/X86/X86TargetAsmInfo.cpp
index 5a60bce..c33b765 100644
--- a/lib/Target/X86/X86TargetAsmInfo.cpp
+++ b/lib/Target/X86/X86TargetAsmInfo.cpp
@@ -283,7 +283,7 @@
case SectionKind::RODataMergeStr:
return ".rdata$linkonce" + GV->getName();
default:
- LLVM_UNREACHABLE("Unknown section kind");
+ llvm_unreachable("Unknown section kind");
}
return NULL;
}