assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 6fa05fc..977e621 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -338,7 +338,7 @@
bool rev = false;
bool inv = false;
switch(CC) {
- default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
+ default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!");
case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
Opc = Alpha::CMPTEQ; break;
case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
@@ -472,7 +472,7 @@
} else if (TypeOperands[i] == MVT::f64) {
Opc = Alpha::STT;
} else
- assert(0 && "Unknown operand");
+ LLVM_UNREACHABLE("Unknown operand");
SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64),
@@ -489,7 +489,7 @@
CallOperands[i], InFlag);
InFlag = Chain.getValue(1);
} else
- assert(0 && "Unknown operand");
+ LLVM_UNREACHABLE("Unknown operand");
}
// Finally, once everything is in registers to pass to the call, emit the
@@ -512,7 +512,7 @@
std::vector<SDValue> CallResults;
switch (N->getValueType(0).getSimpleVT()) {
- default: assert(0 && "Unexpected ret value!");
+ default: LLVM_UNREACHABLE("Unexpected ret value!");
case MVT::Other: break;
case MVT::i64:
Chain = CurDAG->getCopyFromReg(Chain, dl,
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 49fb262..2893536 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -380,7 +380,7 @@
for (unsigned i = 0, e = Args.size(); i != e; ++i)
{
switch (getValueType(Args[i].Ty).getSimpleVT()) {
- default: assert(0 && "Unexpected ValueType for argument!");
+ default: LLVM_UNREACHABLE("Unexpected ValueType for argument!");
case MVT::i1:
case MVT::i8:
case MVT::i16:
@@ -476,7 +476,7 @@
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) {
- default: assert(0 && "Wasn't expecting to be able to lower this!");
+ default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
VarArgsBase,
VarArgsOffset);
@@ -527,7 +527,7 @@
return Lo;
}
case ISD::GlobalTLSAddress:
- assert(0 && "TLS not implemented for Alpha.");
+ LLVM_UNREACHABLE("TLS not implemented for Alpha.");
case ISD::GlobalAddress: {
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
GlobalValue *GV = GSDN->getGlobal();
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 62b5d4c..139a4db 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -332,7 +332,7 @@
case Alpha::FBLE: return Alpha::FBGT;
case Alpha::FBLT: return Alpha::FBGE;
default:
- assert(0 && "Unknown opcode");
+ LLVM_UNREACHABLE("Unknown opcode");
}
return 0; // Not reached
}
diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp
index c62ab75..8919dc0 100644
--- a/lib/Target/Alpha/AlphaJITInfo.cpp
+++ b/lib/Target/Alpha/AlphaJITInfo.cpp
@@ -72,7 +72,7 @@
void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
//FIXME
- assert(0);
+ llvm_unreachable();
}
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
@@ -241,7 +241,7 @@
long idx = 0;
bool doCommon = true;
switch ((Alpha::RelocationType)MR->getRelocationType()) {
- default: assert(0 && "Unknown relocation type!");
+ default: LLVM_UNREACHABLE("Unknown relocation type!");
case Alpha::reloc_literal:
//This is a LDQl
idx = MR->getGOTIndex();
@@ -281,7 +281,7 @@
DOUT << "LDA: " << idx << "\n";
break;
default:
- assert(0 && "Cannot handle gpdist yet");
+ LLVM_UNREACHABLE("Cannot handle gpdist yet");
}
break;
case Alpha::reloc_bsr: {
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 1194a0f..f1e651c 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -307,7 +307,7 @@
}
unsigned AlphaRegisterInfo::getRARegister() const {
- assert(0 && "What is the return address register");
+ LLVM_UNREACHABLE("What is the return address register");
return 0;
}
@@ -316,17 +316,17 @@
}
unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
- assert(0 && "What is the exception register");
+ LLVM_UNREACHABLE("What is the exception register");
return 0;
}
unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
- assert(0 && "What is the exception handler register");
+ LLVM_UNREACHABLE("What is the exception handler register");
return 0;
}
int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
- assert(0 && "What is the dwarf register number");
+ LLVM_UNREACHABLE("What is the dwarf register number");
return -1;
}
diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
index 11f177d..cc278b7 100644
--- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp
@@ -155,7 +155,7 @@
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
- default: assert(0 && "Unknown linkage type!");
+ default: LLVM_UNREACHABLE( "Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;