diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp
index dbb0f86..e6884ab 100644
--- a/lib/CodeGen/InstrSelection/InstrSelection.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp
@@ -220,7 +220,7 @@
   // 
   if (treeRoot->opLabel != VRegListOp)
     {
-      InstructionNode* instrNode = (InstructionNode*) MainTreeNode(treeRoot);
+      InstructionNode* instrNode = (InstructionNode*)treeRoot->treeNodePtr;
       assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
       
       unsigned N = GetInstructionsByRule(instrNode, ruleForNode, nts, Target,
@@ -259,7 +259,7 @@
 	{
 	  assert(i < 2);
 	  InstrTreeNode::InstrTreeNodeType
-	    nodeType = MainTreeNode(kids[i])->getNodeType();
+	    nodeType = kids[i]->treeNodePtr->getNodeType();
 	  if (nodeType == InstrTreeNode::NTVRegListNode ||
 	      nodeType == InstrTreeNode::NTInstructionNode)
 	    {
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 63acea1..e5b768e 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -153,7 +153,8 @@
 // 
 // For the common case of 2- and 3-operand arithmetic/logical instructions,
 // set the m/c instr. operands directly from the VM instruction's operands.
-// Check whether the first or second operand is 0 and can use a dedicated "0" register.
+// Check whether the first or second operand is 0 and can use a dedicated "0"
+// register.
 // Check whether the second operand should use an immediate field or register.
 // (First and third operands are never immediates for such instructions.)
 //