commit c2c64fd3c632df179269db9c80b2d7f071115d2c
author Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 19:52:25 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Fri Nov 11 19:52:25 2005 +0000
tree 9d338e5cf189a65f073491c5fa74254488725018
parent f6947c1bb84f1cd077987fe57f6c33f8319168e7

Fix a bunch more alpha regressions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24304 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 791fced..3218f03 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1533,7 +1533,7 @@
             N.getOperand(0).getValueType() == MVT::f32 &&
             "only f32 to f64 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
-    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
+    BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::ConstantFP: