Revert 147426 because it caused pr11696.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 47b80d0..74ae8a8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -13139,24 +13139,6 @@
}
}
- // The VSELECT instruction is lowered to SSE blend instructions. In many cases
- // the mask is sign-extended to fill the entire lane. However, we only care
- // for the highest bit. Convert sign_extend to srl because it is cheaper.
- // (vselect(sign_extend(x))) -> vselect(srl(x))
- if (N->getOpcode() == ISD::VSELECT &&
- Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) {
- EVT CondVT = Cond.getValueType();
- EVT SExtTy = cast<VTSDNode>(Cond.getOperand(1))->getVT();
- unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() -
- SExtTy.getScalarType().getSizeInBits();
-
- EVT ShiftType = EVT::getVectorVT(*DAG.getContext(),
- MVT::i32, CondVT.getVectorNumElements());
- SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0),
- DAG.getConstant(BitsDiff, ShiftType));
- return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS);
- }
-
return SDValue();
}
diff --git a/test/CodeGen/X86/2011-12-28-vselecti8.ll b/test/CodeGen/X86/2011-12-28-vselecti8.ll
index fc1b83b..dbc122a 100644
--- a/test/CodeGen/X86/2011-12-28-vselecti8.ll
+++ b/test/CodeGen/X86/2011-12-28-vselecti8.ll
@@ -5,10 +5,8 @@
; CHECK: @foo8
; CHECK: psll
-; CHECK-NOT: sra
-; CHECK: pandn
-; CHECK: pand
-; CHECK: or
+; CHECK: psraw
+; CHECK: pblendvb
; CHECK: ret
define void @foo8(float* nocapture %RET) nounwind {
allocas:
diff --git a/test/CodeGen/X86/sext-blend.ll b/test/CodeGen/X86/sext-blend.ll
deleted file mode 100644
index b1f9573..0000000
--- a/test/CodeGen/X86/sext-blend.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -promote-elements -mattr=+sse41 | FileCheck %s
-
-; CHECK: foo
-define <4 x double> @foo(<4 x double> %x, <4 x double> %y) {
- ; CHECK: cmpnlepd
- ; CHECK: psllq
- ; CHECK-NEXT: blendvpd
- ; CHECK: psllq
- ; CHECK-NEXT: blendvpd
- ; CHECK: ret
- %min_is_x = fcmp ult <4 x double> %x, %y
- %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y
- ret <4 x double> %min
-}
-
diff --git a/test/CodeGen/X86/sse2-blend.ll b/test/CodeGen/X86/sse2-blend.ll
index c6602d3..2f4317b 100644
--- a/test/CodeGen/X86/sse2-blend.ll
+++ b/test/CodeGen/X86/sse2-blend.ll
@@ -28,10 +28,10 @@
; Without forcing instructions, fall back to the preferred PS domain.
; CHECK: vsel_i64
-; CHECK: pxor
-; CHECK: and
-; CHECK: andn
-; CHECK: or
+; CHECK: xorps
+; CHECK: andps
+; CHECK: andnps
+; CHECK: orps
; CHECK: ret
define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
@@ -44,10 +44,10 @@
; Without forcing instructions, fall back to the preferred PS domain.
; CHECK: vsel_double
-; CHECK: xor
-; CHECK: and
-; CHECK: andn
-; CHECK: or
+; CHECK: xorps
+; CHECK: andps
+; CHECK: andnps
+; CHECK: orps
; CHECK: ret
define void@vsel_double(<4 x double>* %v1, <4 x double>* %v2) {
diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll
index 0a71dd0..78604a0 100644
--- a/test/CodeGen/X86/sse41-blend.ll
+++ b/test/CodeGen/X86/sse41-blend.ll
@@ -36,7 +36,6 @@
;CHECK: vsel_double
-;CHECK-NOT: sra
;CHECK: blendvpd
;CHECK: ret
define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
@@ -55,7 +54,6 @@
;CHECK: vsel_i8
-;CHECK-NOT: sra
;CHECK: pblendvb
;CHECK: ret
define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -67,7 +65,6 @@
; CHECK: A
define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
; CHECK: cmplepd
- ; CHECK-NOT: sra
; CHECK: blendvpd
%max_is_x = fcmp oge <2 x double> %x, %y
%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
@@ -77,7 +74,6 @@
; CHECK: B
define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
; CHECK: cmpnlepd
- ; CHECK-NOT: sra
; CHECK: blendvpd
%min_is_x = fcmp ult <2 x double> %x, %y
%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y