Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetSubtarget.h b/include/llvm/Target/TargetSubtarget.h
index 64c36d5..f16c9e4 100644
--- a/include/llvm/Target/TargetSubtarget.h
+++ b/include/llvm/Target/TargetSubtarget.h
@@ -15,13 +15,13 @@
#define LLVM_TARGET_TARGETSUBTARGET_H
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/ADT/SmallVector.h"
namespace llvm {
class SDep;
class SUnit;
+class TargetRegisterClass;
+template <typename T> class SmallVectorImpl;
//===----------------------------------------------------------------------===//
///
@@ -38,7 +38,7 @@
// AntiDepBreakMode - Type of anti-dependence breaking that should
// be performed before post-RA scheduling.
typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
- typedef SmallVector<TargetRegisterClass*, 4> ExcludedRCVector;
+ typedef SmallVectorImpl<TargetRegisterClass*> ExcludedRCVector;
virtual ~TargetSubtarget();
@@ -53,12 +53,7 @@
// return true to enable post-register-allocation scheduling.
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
- ExcludedRCVector& ExcludedRCs) const {
- Mode = ANTIDEP_NONE;
- ExcludedRCs.clear();
- return false;
- }
-
+ ExcludedRCVector& ExcludedRCs) const;
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 5917e76..b5729bb 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -216,7 +216,7 @@
// Check for explicit enable/disable of post-ra scheduling.
TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
- TargetSubtarget::ExcludedRCVector ExcludedRCs;
+ SmallVector<TargetRegisterClass*, 4> ExcludedRCs;
if (EnablePostRAScheduler.getPosition() > 0) {
if (!EnablePostRAScheduler)
return false;
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 5af95c3..dc81328 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -16,6 +16,7 @@
#include "llvm/GlobalValue.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/ADT/SmallVector.h"
using namespace llvm;
static cl::opt<bool>
@@ -159,3 +160,13 @@
return false;
}
+
+bool ARMSubtarget::enablePostRAScheduler(
+ CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ ExcludedRCVector& ExcludedRCs) const {
+ Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ ExcludedRCs.clear();
+ ExcludedRCs.push_back(&ARM::GPRRegClass);
+ return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
+}
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index c94f9fe..fd66693 100644
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -127,16 +127,10 @@
const std::string & getCPUString() const { return CPUString; }
- /// enablePostRAScheduler - True at 'More' optimization except
- /// for Thumb1.
+ /// enablePostRAScheduler - True at 'More' optimization.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
- ExcludedRCVector& ExcludedRCs) const {
- Mode = TargetSubtarget::ANTIDEP_CRITICAL;
- ExcludedRCs.clear();
- ExcludedRCs.push_back(&ARM::GPRRegClass);
- return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
- }
+ ExcludedRCVector& ExcludedRCs) const;
/// getInstrItins - Return the instruction itineraies based on subtarget
/// selection.
diff --git a/lib/Target/TargetSubtarget.cpp b/lib/Target/TargetSubtarget.cpp
index 95c92ca..696c09b 100644
--- a/lib/Target/TargetSubtarget.cpp
+++ b/lib/Target/TargetSubtarget.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/ADT/SmallVector.h"
using namespace llvm;
//---------------------------------------------------------------------------
@@ -20,3 +21,13 @@
TargetSubtarget::TargetSubtarget() {}
TargetSubtarget::~TargetSubtarget() {}
+
+bool TargetSubtarget::enablePostRAScheduler(
+ CodeGenOpt::Level OptLevel,
+ AntiDepBreakMode& Mode,
+ ExcludedRCVector& ExcludedRCs) const {
+ Mode = ANTIDEP_NONE;
+ ExcludedRCs.clear();
+ return false;
+}
+
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 9525f04..a7233b5 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -20,6 +20,7 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/ADT/SmallVector.h"
using namespace llvm;
#if defined(_MSC_VER)
@@ -455,3 +456,12 @@
if (StackAlignment)
stackAlignment = StackAlignment;
}
+
+bool X86Subtarget::enablePostRAScheduler(
+ CodeGenOpt::Level OptLevel,
+ TargetSubtarget::AntiDepBreakMode& Mode,
+ ExcludedRCVector& ExcludedRCs) const {
+ Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+ ExcludedRCs.clear();
+ return OptLevel >= CodeGenOpt::Default;
+}
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index f18def1..a0eef05 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -220,11 +220,7 @@
/// at 'More' optimization level.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
- ExcludedRCVector& ExcludedRCs) const {
- Mode = TargetSubtarget::ANTIDEP_CRITICAL;
- ExcludedRCs.clear();
- return OptLevel >= CodeGenOpt::Default;
- }
+ ExcludedRCVector& ExcludedRCs) const;
};
} // End llvm namespace