Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
MMX arguments. This fixes PR4684.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78163 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll
index 8a15978..ede9b59 100644
--- a/test/CodeGen/X86/coalesce-esp.ll
+++ b/test/CodeGen/X86/coalesce-esp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -strict-index-regclass | grep {movl %esp, %eax}
+; RUN: llvm-as < %s | llc | grep {movl %esp, %eax}
; PR4572
; Don't coalesce with %esp if it would end up putting %esp in
diff --git a/test/CodeGen/X86/fast-isel-bc.ll b/test/CodeGen/X86/fast-isel-bc.ll
new file mode 100644
index 0000000..c713387
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-bc.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; PR4684
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.8"
+
+declare void @func2(<1 x i64>)
+
+define void @func1() nounwind {
+
+; This isn't spectacular, but it's MMX code at -O0...
+; CHECK: movl $2, %eax
+; CHECK: movd %rax, %mm0
+; CHECK: movd %mm0, %rdi
+
+ call void @func2(<1 x i64> <i64 2>)
+ ret void
+}
diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll
index 832886b..114e9bf 100644
--- a/test/CodeGen/X86/stack-color-with-reg.ll
+++ b/test/CodeGen/X86/stack-color-with-reg.ll
@@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
; RUN: grep stackcoloring %t | grep "loads eliminated"
; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5
-; RUN: grep asm-printer %t | grep 180
+; RUN: grep asm-printer %t | grep 182
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1